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Small fixes

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Eddie Hung 2020-02-27 10:29:53 -08:00
parent 78929e8c3d
commit 0f4c1906bb
2 changed files with 8 additions and 8 deletions
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12
README.md
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@ -364,13 +364,13 @@ Verilog Attributes and non-standard features
it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
from inserting another pad cell on it. from inserting another pad cell on it.
- The module attribute ``abc9_lut`` is an integer attribute marking to `abc9` - The module attribute ``abc9_lut`` is an integer attribute indicating to
that this module describes a LUT with propagation delays described using `abc9` that this module describes a LUT with an area cost of this value, and
`specify` statements. propagation delays described using `specify` statements.
- The module attribute ``abc9_box`` is a boolean specifying a blackbox or - The module attribute ``abc9_box`` is a boolean specifying a black/white-box
whitebox definition, with propagation delays described using `specify` definition, with propagation delays described using `specify` statements, for
statements, for use by `abc9`. use by `abc9`.
- The port attribute ``abc9_carry`` marks the carry-in (if an input port) and - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
carry-out (if output port) ports of a box. This information is necessary for carry-out (if output port) ports of a box. This information is necessary for

4
kernel/timinginfo.h
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@ -18,8 +18,8 @@
* *
*/ */
#ifndef TIMINGARCS_H #ifndef TIMINGINFO_H
#define TIMINGARCS_H #define TIMINGINFO_H
#include "kernel/yosys.h" #include "kernel/yosys.h"