mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-26 02:25:35 +00:00
Added "design" command (-reset, -save, -load)
This commit is contained in:
parent
974b6a947c
commit
0f38008ed3
6 changed files with 246 additions and 12 deletions
|
@ -896,6 +896,21 @@ void AstModule::update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes)
|
|||
delete newmod;
|
||||
}
|
||||
|
||||
RTLIL::Module *AstModule::clone() const
|
||||
{
|
||||
AstModule *new_mod = new AstModule;
|
||||
cloneInto(new_mod);
|
||||
|
||||
new_mod->ast = ast->clone();
|
||||
new_mod->nolatches = nolatches;
|
||||
new_mod->nomem2reg = nomem2reg;
|
||||
new_mod->mem2reg = mem2reg;
|
||||
new_mod->lib = lib;
|
||||
new_mod->noopt = noopt;
|
||||
|
||||
return new_mod;
|
||||
}
|
||||
|
||||
// internal dummy line number callbacks
|
||||
namespace {
|
||||
int internal_line_num;
|
||||
|
|
|
@ -205,6 +205,7 @@ namespace AST
|
|||
virtual ~AstModule();
|
||||
virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
|
||||
virtual void update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes);
|
||||
virtual RTLIL::Module *clone() const;
|
||||
};
|
||||
|
||||
// this must be set by the language frontend before parsing the sources
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue