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Merge remote-tracking branch 'upstream/master'

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Bogdan Vukobratovic 2019-06-27 12:11:47 +02:00
commit 0f32cb4e0a
37 changed files with 1632 additions and 144 deletions
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3
tests/aiger/.gitignore vendored
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@ -1,2 +1 @@
*.log
*.out
/*_ref.v

28
tests/memories/issue00335.v Normal file
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@ -0,0 +1,28 @@
// expect-wr-ports 1
// expect-rd-ports 1
// expect-rd-clk \clk
module ram2 (input clk,
input sel,
input we,
input [SIZE-1:0] adr,
input [63:0] dat_i,
output reg [63:0] dat_o);
parameter SIZE = 5; // Address size
reg [63:0] mem [0:(1 << SIZE)-1];
integer i;
initial begin
for (i = 0; i < (1<<SIZE) - 1; i = i + 1)
mem[i] <= 0;
end
always @(posedge clk)
if (sel) begin
if (~we)
dat_o <= mem[adr];
else
mem[adr] <= dat_i;
end
endmodule

17
tests/memories/issue00710.v Normal file
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@ -0,0 +1,17 @@
// expect-wr-ports 1
// expect-rd-ports 1
// expect-rd-clk \clk
module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
reg [7:0] bram[0:255];
(* keep *) reg dummy;
always @(posedge clk)
if (reset)
dummy <= 1'b0;
else if (re)
rdata <= bram[addr];
else if (we)
bram[addr] <= wdata;
endmodule

6
tests/memories/run-test.sh
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@ -14,7 +14,7 @@ shift "$((OPTIND-1))"
bash ../tools/autotest.sh $seed -G *.v
for f in `egrep -l 'expect-(wr|rd)-ports' *.v`; do
for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
echo -n "Testing expectations for $f .."
../../yosys -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem" $f
if grep -q expect-wr-ports $f; then
@ -25,6 +25,10 @@ for f in `egrep -l 'expect-(wr|rd)-ports' *.v`; do
grep -q "parameter \\\\RD_PORTS $(gawk '/expect-rd-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
{ echo " ERROR: Unexpected number of read ports."; false; }
fi
if grep -q expect-rd-clk $f; then
grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
{ echo " ERROR: Unexpected read clock."; false; }
fi
echo " ok."
done

11
tests/simple/generate.v
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@ -148,3 +148,14 @@ generate
endgenerate
assign out = steps[WIDTH].outer[0].val;
endmodule
// ------------------------------------------
module gen_test6(output [3:0] o);
generate
genvar i;
for (i = 3; i >= 0; i = i-1) begin
assign o[i] = 1'b0;
end
endgenerate
endmodule

3
tests/various/.gitignore vendored
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@ -1 +1,2 @@
*.log
/*.log
/*.out

141
tests/various/muxcover.ys
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@ -13,7 +13,7 @@ read_verilog -formal <<EOT
EOT
## Examle usage for "pmuxtree" and "muxcover"
## Example usage for "pmuxtree" and "muxcover"
proc
pmuxtree
@ -49,3 +49,142 @@ hierarchy -top equiv
equiv_simple -undef
equiv_status -assert
## Partial matching MUX4
design -reset
read_verilog -formal <<EOT
module mux_if_bal_3_1 #(parameter N=3, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {{W{{1'bx}}}};
if (s[0] == 1'b0)
if (s[1] == 1'b0)
o <= i[0*W+:W];
else
o <= i[1*W+:W];
else
if (s[1] == 1'b0)
o <= i[2*W+:W];
end
endmodule
EOT
prep
design -save gold
techmap
muxcover -mux4=150
select -assert-count 0 t:$_MUX_
select -assert-count 1 t:$_MUX4_
select -assert-count 0 t:$_MUX8_
select -assert-count 0 t:$_MUX16_
techmap -map +/simcells.v t:$_MUX4_
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
## Partial matching MUX8
design -reset
read_verilog -formal <<EOT
module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {{W{{1'bx}}}};
if (s[0] == 1'b0)
if (s[1] == 1'b0)
if (s[2] == 1'b0)
o <= i[0*W+:W];
else
o <= i[1*W+:W];
else
if (s[2] == 1'b0)
o <= i[2*W+:W];
else
o <= i[3*W+:W];
else
if (s[1] == 1'b0)
if (s[2] == 1'b0)
o <= i[4*W+:W];
end
endmodule
EOT
prep
design -save gold
techmap
muxcover -mux4=150 -mux8=200
clean
opt_expr -mux_bool
select -assert-count 0 t:$_MUX_
select -assert-count 0 t:$_MUX4_
select -assert-count 1 t:$_MUX8_
select -assert-count 0 t:$_MUX16_
techmap -map +/simcells.v t:$_MUX8_
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
## Partial matching MUX16
design -reset
read_verilog -formal <<EOT
module mux_if_bal_9_1 #(parameter N=9, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {{W{{1'bx}}}};
if (s[0] == 1'b0)
if (s[1] == 1'b0)
if (s[2] == 1'b0)
if (s[3] == 1'b0)
o <= i[0*W+:W];
else
o <= i[1*W+:W];
else
if (s[3] == 1'b0)
o <= i[2*W+:W];
else
o <= i[3*W+:W];
else
if (s[2] == 1'b0)
if (s[3] == 1'b0)
o <= i[4*W+:W];
else
o <= i[5*W+:W];
else
if (s[3] == 1'b0)
o <= i[6*W+:W];
else
o <= i[7*W+:W];
else
if (s[1] == 1'b0)
if (s[2] == 1'b0)
if (s[3] == 1'b0)
o <= i[8*W+:W];
end
endmodule
EOT
prep
design -save gold
techmap
muxcover -mux4=150 -mux8=200 -mux16=250
clean
opt_expr -mux_bool
select -assert-count 0 t:$_MUX_
select -assert-count 0 t:$_MUX4_
select -assert-count 0 t:$_MUX8_
select -assert-count 1 t:$_MUX16_
techmap -map +/simcells.v t:$_MUX16_
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter

259
tests/various/muxpack.v Normal file
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module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @*
if (s == 0) o <= i[0*W+:W];
else if (s == 1) o <= i[1*W+:W];
else if (s == 2) o <= i[2*W+:W];
else if (s == 3) o <= i[3*W+:W];
else o <= {W{1'bx}};
endmodule
module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {W{1'bx}};
if (s == 0) o <= i[0*W+:W];
if (s == 1) o <= i[1*W+:W];
if (s == 2) o <= i[2*W+:W];
if (s == 3) o <= i[3*W+:W];
if (s == 4) o <= i[4*W+:W];
end
endmodule
module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @*
if (s != 0)
if (s != 1)
if (s != 2)
if (s != 3)
if (s != 4) o <= i[4*W+:W];
else o <= i[0*W+:W];
else o <= i[3*W+:W];
else o <= i[2*W+:W];
else o <= i[1*W+:W];
else o <= {W{1'bx}};
endmodule
module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {W{1'bx}};
if (s == 0) o <= i[0*W+:W];
if (s == 1) o <= i[1*W+:W];
if (s == 2) o[W-2:0] <= i[2*W+:W-1];
if (s == 3) o <= i[3*W+:W];
if (s == 4) o <= i[4*W+:W];
end
endmodule
module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
if (s == 0) o <= i[0*W+:W];
// else if (s == 1) o <= i[1*W+:W];
// else if (s == 2) o <= i[2*W+:W];
else if (s == 3) o <= i[3*W+:W];
else o <= {W{1'bx}};
end
endmodule
module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {W{1'bx}};
if (s == 3) o <= i[3*W+:W];
if (s == 2) o <= i[2*W+:W];
if (s == 1) o <= i[1*W+:W];
if (s == 4) o <= i[4*W+:W];
if (s == 0) o <= i[0*W+:W];
end
endmodule
module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @*
if (s == 0) o <= i[0*W+:W];
else if (s == 1) o <= i[1*W+:W];
else if (s == 2) o <= i[2*W+:W];
else if (s == 3) o <= i[3*W+:W];
else if (s == 0) o <= {W{1'b0}};
else o <= {W{1'bx}};
endmodule
module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {W{1'bx}};
if (s == 0) o <= i[0*W+:W];
if (s == 1) o <= i[1*W+:W];
if (s == 2) o <= i[2*W+:W];
if (s == 3) o <= i[3*W+:W];
if (s == 4) o <= i[4*W+:W];
if (s == 0) o <= i[2*W+:W];
end
endmodule
module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {W{1'bx}};
case (s)
0: o <= i[0*W+:W];
default:
case (s)
1: o <= i[1*W+:W];
2: o <= i[2*W+:W];
default:
case (s)
3: o <= i[3*W+:W];
4: o <= i[4*W+:W];
5: o <= i[5*W+:W];
default:
case (s)
6: o <= i[6*W+:W];
default: o <= i[7*W+:W];
endcase
endcase
endcase
endcase
end
endmodule
module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @*
if (s[0] == 1'b0)
if (s[1] == 1'b0)
if (s[2] == 1'b0)
o <= i[0*W+:W];
else
o <= i[1*W+:W];
else
if (s[2] == 1'b0)
o <= i[2*W+:W];
else
o <= i[3*W+:W];
else
if (s[1] == 1'b0)
if (s[2] == 1'b0)
o <= i[4*W+:W];
else
o <= i[5*W+:W];
else
if (s[2] == 1'b0)
o <= i[6*W+:W];
else
o <= i[7*W+:W];
endmodule
module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @*
if (s[0] == 1'b0)
if (s[1] == 1'b0)
if (s[2] == 1'b0)
o <= i[0*W+:W];
else
o <= i[1*W+:W];
else
if (s[2] == 1'b0)
o <= i[2*W+:W];
else
o <= i[3*W+:W];
else
o <= i[4*W+:W];
endmodule
module cliffordwolf_nonexclusive_select (
input wire x, y, z,
input wire a, b, c, d,
output reg o
);
always @* begin
o = a;
if (x) o = b;
if (y) o = c;
if (z) o = d;
end
endmodule
module cliffordwolf_freduce (
input wire [1:0] s,
input wire a, b, c, d,
output reg [3:0] o
);
always @* begin
o = {4{a}};
if (s == 0) o = {3{b}};
if (s == 1) o = {2{c}};
if (s == 2) o = d;
end
endmodule
module case_nonexclusive_select (
input wire [1:0] x, y,
input wire a, b, c, d, e,
output reg o
);
always @* begin
case (x)
0: o = b;
2: o = b;
1: o = c;
default: begin
o = a;
if (y == 0) o = d;
if (y == 1) o = e;
end
endcase
end
endmodule
module case_nonoverlap (
input wire [2:0] x,
input wire a, b, c, d, e,
output reg o
);
always @* begin
case (x)
0, 2: o = b; // Creates $reduce_or
1: o = c;
default:
case (x)
3: o = d; 4: o = d; // Creates $reduce_or
5: o = e;
default: o = 1'b0;
endcase
endcase
end
endmodule
module case_overlap (
input wire [2:0] x,
input wire a, b, c, d, e,
output reg o
);
always @* begin
case (x)
0, 2: o = b; // Creates $reduce_or
1: o = c;
default:
case (x)
0: o = 1'b1; // OVERLAP!
3, 4: o = d; // Creates $reduce_or
5: o = e;
default: o = 1'b0;
endcase
endcase
end
endmodule
module case_overlap2 (
input wire [2:0] x,
input wire a, b, c, d, e,
output reg o
);
always @* begin
case (x)
0: o = b; 2: o = b; // Creates $reduce_or
1: o = c;
default:
case (x)
0: o = d; 2: o = d; // Creates $reduce_or
3: o = d; 4: o = d; // Creates $reduce_or
5: o = e;
default: o = 1'b0;
endcase
endcase
end
endmodule

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@ -0,0 +1,268 @@
read_verilog muxpack.v
design -save read
hierarchy -top mux_if_unbal_4_1
prep
design -save gold
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top mux_if_unbal_5_3
prep
design -save gold
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
# TODO: Currently ExclusiveDatabase only analyses $eq cells
#design -load read
#hierarchy -top mux_if_unbal_5_3_invert
#prep
#design -save gold
#muxpack
#opt
#stat
#select -assert-count 0 t:$mux
#select -assert-count 1 t:$pmux
#design -stash gate
#design -import gold -as gold
#design -import gate -as gate
#miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top mux_if_unbal_5_3_width_mismatch
prep
design -save gold
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 2 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top mux_if_unbal_4_1_missing
prep
design -save gold
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top mux_if_unbal_5_3_order
prep
design -save gold
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top mux_if_unbal_4_1_nonexcl
prep
design -save gold
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top mux_if_unbal_5_3_nonexcl
prep
design -save gold
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top mux_case_unbal_8_7
prep
design -save gold
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top mux_if_bal_8_2
prep
design -save gold
muxpack
opt
stat
select -assert-count 7 t:$mux
select -assert-count 0 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top mux_if_bal_5_1
prep
design -save gold
muxpack
opt
stat
select -assert-count 4 t:$mux
select -assert-count 0 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top cliffordwolf_nonexclusive_select
prep
design -save gold
muxpack
opt
stat
select -assert-count 3 t:$mux
select -assert-count 0 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
#design -load read
#hierarchy -top cliffordwolf_freduce
#prep
#design -save gold
#proc; opt; freduce; opt
#show
#muxpack
#opt
#stat
#select -assert-count 0 t:$mux
#select -assert-count 1 t:$pmux
#design -stash gate
#design -import gold -as gold
#design -import gate -as gate
#miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top case_nonexclusive_select
prep
design -save gold
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 2 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top case_nonoverlap
#prep # Do not prep otherwise $pmux's overlapping entry will get removed
proc
design -save gold
opt -fast -mux_undef
select -assert-count 2 t:$pmux
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top case_overlap
#prep # Do not prep otherwise $pmux's overlapping entry will get removed
proc
design -save gold
opt -fast -mux_undef
select -assert-count 2 t:$pmux
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 2 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top case_overlap2
#prep # Do not prep otherwise $pmux's overlapping entry will get removed
proc
design -save gold
opt -fast -mux_undef
select -assert-count 2 t:$pmux
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 2 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter

48
tests/various/shregmap.v Normal file
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module shregmap_static_test(input i, clk, output [1:0] q);
reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;
always @(posedge clk) begin
head <= i;
shift1 <= {shift1[2:0], head};
shift2 <= {shift2[2:0], head};
end
assign q = {shift2[3], shift1[3]};
endmodule
module $__SHREG_DFF_P_(input C, D, output Q);
parameter DEPTH = 1;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
always @(posedge C)
r <= { r[DEPTH-2:0], D };
assign Q = r[DEPTH-1];
endmodule
module shregmap_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q);
reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;
always @(posedge clk) begin
head <= i;
shift1 <= {shift1[2:0], head};
shift2 <= {shift2[2:0], head};
end
assign q = {shift2[l2], shift1[l1]};
endmodule
module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
parameter CLKPOL = 1;
parameter ENPOL = 1;
parameter DEPTH = 1;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;
always @(posedge C)
r <= { r[DEPTH-2:0], D };
assign Q = r[L];
endmodule

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read_verilog shregmap.v
design -save read
design -copy-to model $__SHREG_DFF_P_
hierarchy -top shregmap_static_test
prep
design -save gold
techmap
shregmap -init
opt
stat
# show -width
select -assert-count 1 t:$_DFF_P_
select -assert-count 2 t:$__SHREG_DFF_P_
design -stash gate
design -import gold -as gold
design -import gate -as gate
design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_
prep
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -seq 5 miter
design -load gold
stat
design -load gate
stat
##########
design -load read
design -copy-to model $__XILINX_SHREG_
hierarchy -top shregmap_variable_test
prep
design -save gold
simplemap t:$dff t:$dffe
shregmap -tech xilinx
stat
# show -width
write_verilog -noexpr -norename
select -assert-count 1 t:$_DFF_P_
select -assert-count 2 t:$__XILINX_SHREG_
design -stash gate
design -import gold -as gold
design -import gate -as gate
design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
prep
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -seq 5 miter
design -load gold
stat
design -load gate
stat

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read_verilog -formal <<EOT
module gate(input clk, output [32:0] o, p, q, r, s, t, u);
assign o = 'bx;
assign p = 1'bx;
assign q = 'bz;
assign r = 1'bz;
assign s = 1'b0;
assign t = 'b1;
assign u = -'sb1;
endmodule
EOT
proc
## Equivalence checking
read_verilog -formal <<EOT
module gold(input clk, output [32:0] o, p, q, r, s, t, u);
assign o = {33{1'bx}};
assign p = {{32{1'b0}}, 1'bx};
assign q = {33{1'bz}};
assign r = {{32{1'b0}}, 1'bz};
assign s = {33{1'b0}};
assign t = {{32{1'b0}}, 1'b1};
assign u = {33{1'b1}};
endmodule
EOT
proc
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -enable_undef miter