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https://github.com/YosysHQ/yosys
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Added sequential solving support to sat_solve
This commit is contained in:
Clifford Wolf
parent
6f330f0132
commit
0efde13775
3 changed files with 261 additions and 93 deletions
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@ -4,3 +4,4 @@ sat_solve -set y 1'b1 example001
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sat_solve -set y 1'b1 example002
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sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
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sat_solve -set y 1'b1 example004
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sat_solve -show rst,counter -set-at 3 y 1'b1 -seq 4 example004
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@ -130,12 +130,25 @@ struct SatSolvePass : public Pass {
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log(" show the model for the specified signal. if no -show option is\n");
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log(" passed then a set of signals to be shown is automatically selected.\n");
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log("\n");
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log("The following options can be used to set up a sequential problem:\n");
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log("\n");
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log(" -seq <N>\n");
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log(" set up a sequential problem with <N> time steps. The steps will\n");
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log(" be numbered from 1 to N.\n");
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log("\n");
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log(" -set-at <N> <signal> <value>\n");
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log(" -unset-at <N> <signal>\n");
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log(" set or unset the specified signal to the specified value in the\n");
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log(" given timestep. this has priority over a -set for the same signal.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::vector<std::pair<std::string, std::string>> sets;
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std::map<int, std::vector<std::pair<std::string, std::string>>> sets_at;
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std::map<int, std::vector<std::string>> unsets_at;
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std::vector<std::string> shows;
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int loopcount = 0;
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int loopcount = 0, seq_len = 0;
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log_header("Executing SAT_SOLVE pass (solving SAT problems in the circuit).\n");
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@ -155,6 +168,23 @@ struct SatSolvePass : public Pass {
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sets.push_back(std::pair<std::string, std::string>(lhs, rhs));
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continue;
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}
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if (args[argidx] == "-seq" && argidx+1 < args.size()) {
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seq_len = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-set-at" && argidx+3 < args.size()) {
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int timestep = atoi(args[++argidx].c_str());
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std::string lhs = args[++argidx].c_str();
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std::string rhs = args[++argidx].c_str();
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sets_at[timestep].push_back(std::pair<std::string, std::string>(lhs, rhs));
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continue;
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}
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if (args[argidx] == "-unset-at" && argidx+2 < args.size()) {
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int timestep = atoi(args[++argidx].c_str());
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std::string lhs = args[++argidx].c_str();
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unsets_at[timestep].push_back(lhs);
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continue;
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}
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if (args[argidx] == "-show" && argidx+1 < args.size()) {
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shows.push_back(args[++argidx]);
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continue;
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@ -186,47 +216,119 @@ struct SatSolvePass : public Pass {
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std::map<RTLIL::Cell*,RTLIL::SigSpec> show_driven;
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CellTypes ct(design);
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for (auto &s : sets)
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for (int timestep = -1; timestep <= seq_len; timestep++)
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{
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RTLIL::SigSpec lhs, rhs;
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// set timestep=-1 for non-seq problems and timestep=1:N for seq problems
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if ((timestep == -1 && seq_len > 0) || timestep == 0)
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continue;
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if (!parse_sigstr(lhs, module, s.first))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
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if (!parse_sigstr(rhs, module, s.second))
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log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
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show_signal_pool.add(sigmap(lhs));
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show_signal_pool.add(sigmap(rhs));
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if (timestep > 0)
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log ("\nSetting up time step %d:\n", timestep);
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else
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log ("\nSetting up SAT problem:\n");
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if (lhs.width != rhs.width)
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log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
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s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
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RTLIL::SigSpec big_lhs, big_rhs;
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log("Import constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
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for (auto &s : sets)
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{
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RTLIL::SigSpec lhs, rhs;
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std::vector<int> lhs_vec = satgen.importSigSpec(lhs);
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std::vector<int> rhs_vec = satgen.importSigSpec(rhs);
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if (!parse_sigstr(lhs, module, s.first))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
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if (!parse_sigstr(rhs, module, s.second))
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log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
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show_signal_pool.add(sigmap(lhs));
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show_signal_pool.add(sigmap(rhs));
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if (lhs.width != rhs.width)
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log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
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s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
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log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
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big_lhs.remove2(lhs, &big_rhs);
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big_lhs.append(lhs);
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big_rhs.append(rhs);
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}
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for (auto &s : sets_at[timestep])
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{
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RTLIL::SigSpec lhs, rhs;
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if (!parse_sigstr(lhs, module, s.first))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
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if (!parse_sigstr(rhs, module, s.second))
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log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
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show_signal_pool.add(sigmap(lhs));
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show_signal_pool.add(sigmap(rhs));
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if (lhs.width != rhs.width)
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log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
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s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
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log("Import set-constraint for timestep: %s = %s\n", log_signal(lhs), log_signal(rhs));
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big_lhs.remove2(lhs, &big_rhs);
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big_lhs.append(lhs);
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big_rhs.append(rhs);
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}
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for (auto &s : unsets_at[timestep])
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{
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RTLIL::SigSpec lhs;
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if (!parse_sigstr(lhs, module, s))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.c_str());
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show_signal_pool.add(sigmap(lhs));
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log("Import unset-constraint for timestep: %s\n", log_signal(lhs));
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big_lhs.remove2(lhs, &big_rhs);
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}
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log("Final constraint equation: %s = %s\n", log_signal(big_lhs), log_signal(big_rhs));
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std::vector<int> lhs_vec = satgen.importSigSpec(big_lhs, timestep);
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std::vector<int> rhs_vec = satgen.importSigSpec(big_rhs, timestep);
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ez.assume(ez.vec_eq(lhs_vec, rhs_vec));
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int import_cell_counter = 0;
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for (auto &c : module->cells)
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if (design->selected(module, c.second) && ct.cell_known(c.second->type)) {
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// log("Import cell: %s\n", RTLIL::id2cstr(c.first));
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if (satgen.importCell(c.second, timestep)) {
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for (auto &p : c.second->connections)
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if (ct.cell_output(c.second->type, p.first))
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show_drivers.insert(sigmap(p.second), c.second);
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else
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show_driven[c.second].append(sigmap(p.second));
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import_cell_counter++;
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} else
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log("Warning: failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
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}
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log("Imported %d cells to SAT database.\n", import_cell_counter);
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}
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int import_cell_counter = 0;
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for (auto &c : module->cells)
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if (design->selected(module, c.second) && ct.cell_known(c.second->type)) {
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// log("Import cell: %s\n", RTLIL::id2cstr(c.first));
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if (satgen.importCell(c.second)) {
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for (auto &p : c.second->connections)
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if (ct.cell_output(c.second->type, p.first))
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show_drivers.insert(sigmap(p.second), c.second);
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else
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show_driven[c.second].append(sigmap(p.second));
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import_cell_counter++;
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} else
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log("Warning: failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
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struct ModelBlockInfo {
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int timestep, offset, width;
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std::string description;
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bool operator < (const ModelBlockInfo &other) const {
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if (timestep != other.timestep)
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return timestep < other.timestep;
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if (description != other.description)
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return description < other.description;
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if (offset != other.offset)
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return offset < other.offset;
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if (width != other.width)
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return width < other.width;
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return false;
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}
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log("Imported %d cells to SAT database.\n", import_cell_counter);
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};
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RTLIL::SigSpec modelSig;
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std::vector<int> modelExpressions;
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std::vector<bool> modelValues;
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std::set<ModelBlockInfo> modelInfo;
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// Add "normal" show signals for every timestep
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RTLIL::SigSpec modelSig;
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if (shows.size() == 0) {
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SigPool handled_signals, final_signals;
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@ -256,52 +358,100 @@ struct SatSolvePass : public Pass {
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}
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}
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modelSig.expand();
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modelSig.sort_and_unify();
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// log("Model signals: %s\n", log_signal(modelSig));
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for (auto &c : modelSig.chunks)
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if (c.wire != NULL) {
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ModelBlockInfo info;
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RTLIL::SigSpec chunksig = c;
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std::vector<int> vec = satgen.importSigSpec(chunksig);
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log_assert(vec.size() == 1);
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modelExpressions.push_back(vec[0]);
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info.width = chunksig.width;
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info.description = log_signal(chunksig);
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for (int timestep = -1; timestep <= seq_len; timestep++) {
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if ((timestep == -1 && seq_len > 0) || timestep == 0)
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continue;
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std::vector<int> vec = satgen.importSigSpec(chunksig, timestep);
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info.timestep = timestep;
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info.offset = modelExpressions.size();
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modelExpressions.insert(modelExpressions.end(), vec.begin(), vec.end());
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modelInfo.insert(info);
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}
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}
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// Add zero step signals as collected by satgen
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modelSig = satgen.initial_signals.export_all();
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for (auto &c : modelSig.chunks)
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if (c.wire != NULL) {
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ModelBlockInfo info;
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RTLIL::SigSpec chunksig = c;
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info.timestep = 0;
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info.offset = modelExpressions.size();
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info.width = chunksig.width;
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info.description = log_signal(chunksig);
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std::vector<int> vec = satgen.importSigSpec(chunksig, 1);
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modelExpressions.insert(modelExpressions.end(), vec.begin(), vec.end());
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modelInfo.insert(info);
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}
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#if 0
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// print CNF for debugging
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ez.printDIMACS(stdout, true);
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#endif
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rerun_solver:
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log("Solving problem with %d variables and %d clauses..\n", ez.numCnfVariables(), ez.numCnfClauses());
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log("\nSolving problem with %d variables and %d clauses..\n", ez.numCnfVariables(), ez.numCnfClauses());
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if (ez.solve(modelExpressions, modelValues))
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{
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log("SAT solving finished - model found:\n\n");
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log("SAT solving finished - model found:\n");
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log("\n");
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int modelIdx = 0;
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int maxModelName = 10;
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int maxModelWidth = 10;
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modelSig.optimize();
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for (auto &c : modelSig.chunks)
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if (c.wire != NULL) {
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maxModelName = std::max(maxModelName, int(c.wire->name.size()));
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maxModelWidth = std::max(maxModelWidth, c.width);
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}
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const char *hline = "--------------------------------------------------------";
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log(" %-*s %10s %10s %*s\n", maxModelName+10, "Signal Name", "Dec", "Hex", maxModelWidth+5, "Bin");
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log(" %*.*s %10.10s %10.10s %*.*s\n", maxModelName+10, maxModelName+10,
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hline, hline, hline, maxModelWidth+5, maxModelWidth+5, hline);
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for (auto &c : modelSig.chunks) {
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if (c.wire == NULL)
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continue;
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RTLIL::Const value;
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for (int i = 0; i < c.width; i++)
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value.bits.push_back(modelValues.at(modelIdx+i) ? RTLIL::State::S1 : RTLIL::State::S0);
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if (c.width <= 32)
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log(" %-*s %10d %10x %*s\n", maxModelName+10, log_signal(c), value.as_int(), value.as_int(), maxModelWidth+5, value.as_string().c_str());
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else
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log(" %-*s %10s %10s %*s\n", maxModelName+10, log_signal(c), "--", "--", maxModelWidth+5, value.as_string().c_str());
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modelIdx += c.width;
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for (auto &info : modelInfo) {
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maxModelName = std::max(maxModelName, int(info.description.size()));
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maxModelWidth = std::max(maxModelWidth, info.width);
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}
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int last_timestep = -2;
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for (auto &info : modelInfo)
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{
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RTLIL::Const value;
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for (int i = 0; i < info.width; i++)
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value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
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if (info.timestep != last_timestep) {
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const char *hline = "--------------------------------------------------------";
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if (last_timestep == -2) {
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log(seq_len > 0 ? " Time " : " ");
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log("%-*s %10s %10s %*s\n", maxModelName+10, "Signal Name", "Dec", "Hex", maxModelWidth+5, "Bin");
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}
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log(seq_len > 0 ? " ---- " : " ");
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log("%*.*s %10.10s %10.10s %*.*s\n", maxModelName+10, maxModelName+10,
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hline, hline, hline, maxModelWidth+5, maxModelWidth+5, hline);
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last_timestep = info.timestep;
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}
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if (seq_len > 0) {
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if (info.timestep > 0)
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log(" %4d ", info.timestep);
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else
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log(" init ");
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} else
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log(" ");
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if (info.width <= 32)
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log("%-*s %10d %10x %*s\n", maxModelName+10, info.description.c_str(), value.as_int(), value.as_int(), maxModelWidth+5, value.as_string().c_str());
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else
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log("%-*s %10s %10s %*s\n", maxModelName+10, info.description.c_str(), "--", "--", maxModelWidth+5, value.as_string().c_str());
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}
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if (last_timestep == -2)
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log(" no model variables selected for display.\n");
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if (loopcount != 0) {
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log("\n");
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std::vector<int> clause;
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for (size_t i = 0; i < modelExpressions.size(); i++)
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clause.push_back(modelValues.at(i) ? ez.NOT(modelExpressions.at(i)) : modelExpressions.at(i));
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