mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-04 02:10:24 +00:00
pmgen: Move passes out of pmgen folder
- Techlib pmgens are now in relevant techlibs/*. - `peepopt` pmgens are now in passes/opt. - `test_pmgen` is still in passes/pmgen. - Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location, as well as the `#include`s. - Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the top level Makefile. - Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir $@))`.
This commit is contained in:
Krystine Sherwin
parent
18a7c00382
commit
0ec5f1b756
31 changed files with 71 additions and 77 deletions
326
techlibs/xilinx/xilinx_srl.pmg
Normal file
326
techlibs/xilinx/xilinx_srl.pmg
Normal file
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@ -0,0 +1,326 @@
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pattern fixed
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state <IdString> clk_port en_port
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udata <vector<Cell*>> chain longest_chain
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udata <pool<Cell*>> non_first_cells
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udata <int> minlen
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code
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non_first_cells.clear();
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subpattern(setup);
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endcode
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match first
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select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
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select !first->has_keep_attr()
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select !first->type.in(\FDRE) || !param(first, \IS_R_INVERTED).as_bool()
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select !first->type.in(\FDRE) || !param(first, \IS_D_INVERTED).as_bool()
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select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero()
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filter !non_first_cells.count(first)
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generate
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SigSpec C = module->addWire(NEW_ID);
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SigSpec D = module->addWire(NEW_ID);
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SigSpec Q = module->addWire(NEW_ID);
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auto r = rng(8);
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Cell* cell;
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switch (r)
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{
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case 0:
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case 1:
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cell = module->addCell(NEW_ID, \FDRE);
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cell->setPort(\C, C);
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cell->setPort(\D, D);
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cell->setPort(\Q, Q);
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cell->setPort(\CE, module->addWire(NEW_ID));
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if (r & 1)
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cell->setPort(\R, module->addWire(NEW_ID));
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else {
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if (rng(2) == 0)
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cell->setPort(\R, State::S0);
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}
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break;
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case 2:
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case 3:
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cell = module->addDffGate(NEW_ID, C, D, Q, r & 1);
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break;
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case 4:
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case 5:
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case 6:
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case 7:
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cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 2);
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break;
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default: log_abort();
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}
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endmatch
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code clk_port en_port
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if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1))
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clk_port = \C;
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else log_abort();
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if (first->type.in($_DFF_N_, $_DFF_P_))
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en_port = IdString();
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else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
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en_port = \E;
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else if (first->type.in(\FDRE, \FDRE_1))
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en_port = \CE;
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else log_abort();
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longest_chain.clear();
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chain.push_back(first);
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subpattern(tail);
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finally
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chain.pop_back();
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log_assert(chain.empty());
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if (GetSize(longest_chain) >= minlen)
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accept;
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endcode
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// ------------------------------------------------------------------
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subpattern setup
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arg clk_port
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arg en_port
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match first
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select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
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select !first->has_keep_attr()
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select !first->type.in(\FDRE) || !param(first, \IS_R_INVERTED).as_bool()
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select !first->type.in(\FDRE) || !param(first, \IS_D_INVERTED).as_bool()
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select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero()
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endmatch
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code clk_port en_port
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if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1))
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clk_port = \C;
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else log_abort();
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if (first->type.in($_DFF_N_, $_DFF_P_))
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en_port = IdString();
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else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
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en_port = \E;
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else if (first->type.in(\FDRE, \FDRE_1))
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en_port = \CE;
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else log_abort();
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endcode
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match next
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select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
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select !next->has_keep_attr()
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select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep)
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select nusers(port(next, \Q)) == 2
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index <IdString> next->type === first->type
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index <SigBit> port(next, \Q) === port(first, \D)
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filter port(next, clk_port) == port(first, clk_port)
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filter en_port == IdString() || port(next, en_port) == port(first, en_port)
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filter !first->type.in(\FDRE) || param(next, \IS_C_INVERTED).as_bool() == param(first, \IS_C_INVERTED).as_bool()
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filter !first->type.in(\FDRE) || param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()
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filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()
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filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero()
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endmatch
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code
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non_first_cells.insert(next);
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endcode
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// ------------------------------------------------------------------
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subpattern tail
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arg first
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arg clk_port
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arg en_port
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match next
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semioptional
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select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
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select !next->has_keep_attr()
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select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep)
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select nusers(port(next, \Q)) == 2
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index <IdString> next->type === chain.back()->type
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index <SigBit> port(next, \Q) === port(chain.back(), \D)
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filter port(next, clk_port) == port(first, clk_port)
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filter en_port == IdString() || port(next, en_port) == port(first, en_port)
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filter !first->type.in(\FDRE) || param(next, \IS_C_INVERTED).as_bool() == param(first, \IS_C_INVERTED).as_bool()
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filter !first->type.in(\FDRE) || param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()
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filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()
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filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero()
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generate
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Cell *cell = module->addCell(NEW_ID, chain.back()->type);
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cell->setPort(\C, chain.back()->getPort(\C));
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cell->setPort(\D, module->addWire(NEW_ID));
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cell->setPort(\Q, chain.back()->getPort(\D));
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if (cell->type == \FDRE) {
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if (rng(2) == 0)
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cell->setPort(\R, port(chain.back(), \R, State::S0));
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cell->setPort(\CE, chain.back()->getPort(\CE));
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}
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else if (cell->type.begins_with("$_DFFE_"))
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cell->setPort(\E, chain.back()->getPort(\E));
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endmatch
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code
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if (next) {
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chain.push_back(next);
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subpattern(tail);
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} else {
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if (GetSize(chain) > GetSize(longest_chain))
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longest_chain = chain;
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}
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finally
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if (next)
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chain.pop_back();
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endcode
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// -----------
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pattern variable
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state <IdString> clk_port en_port
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state <int> shiftx_width
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state <int> slice
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udata <int> minlen
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udata <vector<pair<Cell*,int>>> chain
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udata <pool<SigBit>> chain_bits
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code
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chain_bits.clear();
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endcode
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match shiftx
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select shiftx->type.in($shiftx)
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select !shiftx->has_keep_attr()
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select param(shiftx, \Y_WIDTH).as_int() == 1
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filter param(shiftx, \A_WIDTH).as_int() >= minlen
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generate
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minlen = 3;
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module->addShiftx(NEW_ID, module->addWire(NEW_ID, rng(6)+minlen), module->addWire(NEW_ID, 3), module->addWire(NEW_ID));
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endmatch
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code shiftx_width
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shiftx_width = param(shiftx, \A_WIDTH).as_int();
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endcode
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match first
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select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
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select !first->has_keep_attr()
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select port(first, \Q)[0].wire && !port(first, \Q)[0].wire->get_bool_attribute(\keep)
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slice idx GetSize(port(first, \Q))
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select nusers(port(first, \Q)[idx]) <= 2
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index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1]
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set slice idx
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generate
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SigSpec C = module->addWire(NEW_ID);
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auto WIDTH = rng(3)+1;
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SigSpec D = module->addWire(NEW_ID, WIDTH);
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SigSpec Q = module->addWire(NEW_ID, WIDTH);
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auto r = rng(8);
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Cell *cell = nullptr;
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switch (r)
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{
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case 0:
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case 1:
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cell = module->addDff(NEW_ID, C, D, Q, r & 1);
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break;
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case 2:
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case 3:
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case 4:
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case 5:
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//cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4);
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//break;
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case 6:
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case 7:
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WIDTH = 1;
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cell = module->addDffGate(NEW_ID, C, D[0], Q[0], r & 1);
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break;
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default: log_abort();
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}
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shiftx->connections_.at(\A)[shiftx_width-1] = port(cell, \Q)[rng(WIDTH)];
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endmatch
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code clk_port en_port
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if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
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clk_port = \C;
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else if (first->type.in($dff, $dffe))
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clk_port = \CLK;
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else log_abort();
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if (first->type.in($_DFF_N_, $_DFF_P_, $dff))
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en_port = IdString();
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else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
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en_port = \E;
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else if (first->type.in($dffe))
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en_port = \EN;
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else log_abort();
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chain_bits.insert(port(first, \Q)[slice]);
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chain.emplace_back(first, slice);
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subpattern(tail);
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finally
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if (GetSize(chain) == shiftx_width)
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accept;
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chain.clear();
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endcode
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// ------------------------------------------------------------------
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subpattern tail
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arg first
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arg shiftx
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arg shiftx_width
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arg slice
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arg clk_port
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arg en_port
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match next
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semioptional
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select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
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select !next->has_keep_attr()
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select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep)
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slice idx GetSize(port(next, \Q))
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select nusers(port(next, \Q)[idx]) <= 3
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index <IdString> next->type === chain.back().first->type
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index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second]
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index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
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filter port(next, clk_port) == port(first, clk_port)
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filter en_port == IdString() || port(next, en_port) == port(first, en_port)
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filter !next->type.in($dff, $dffe) || param(next, \CLK_POLARITY).as_bool() == param(first, \CLK_POLARITY).as_bool()
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filter !next->type.in($dffe) || param(next, \EN_POLARITY).as_bool() == param(first, \EN_POLARITY).as_bool()
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filter !chain_bits.count(port(next, \D)[idx])
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set slice idx
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generate
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if (GetSize(chain) < shiftx_width) {
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auto back = chain.back().first;
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auto slice = chain.back().second;
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if (back->type.in($dff, $dffe)) {
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auto WIDTH = GetSize(port(back, \D));
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if (rng(2) == 0 && slice < WIDTH-1) {
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auto new_slice = slice + rng(WIDTH-1-slice);
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back->connections_.at(\D)[slice] = port(back, \Q)[new_slice];
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}
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else {
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auto D = module->addWire(NEW_ID, WIDTH);
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if (back->type == $dff)
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module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
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else if (back->type == $dffe)
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module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
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else
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log_abort();
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}
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}
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else if (back->type.begins_with("$_DFF_")) {
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Cell *cell = module->addCell(NEW_ID, back->type);
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cell->setPort(\C, back->getPort(\C));
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cell->setPort(\D, module->addWire(NEW_ID));
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cell->setPort(\Q, back->getPort(\D));
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}
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else
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log_abort();
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shiftx->connections_.at(\A)[shiftx_width-1-GetSize(chain)] = port(back, \D)[slice];
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}
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endmatch
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code
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if (next) {
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chain_bits.insert(port(next, \Q)[slice]);
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chain.emplace_back(next, slice);
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if (GetSize(chain) < shiftx_width)
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subpattern(tail);
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}
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endcode
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