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pmgen: Move passes out of pmgen folder
- Techlib pmgens are now in relevant techlibs/*. - `peepopt` pmgens are now in passes/opt. - `test_pmgen` is still in passes/pmgen. - Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location, as well as the `#include`s. - Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the top level Makefile. - Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir $@))`.
This commit is contained in:
Krystine Sherwin
parent
18a7c00382
commit
0ec5f1b756
31 changed files with 71 additions and 77 deletions
409
techlibs/xilinx/xilinx_dsp_cascade.pmg
Normal file
409
techlibs/xilinx/xilinx_dsp_cascade.pmg
Normal file
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@ -0,0 +1,409 @@
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// This file describes the third of three pattern matcher setups that
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// forms the `xilinx_dsp` pass described in xilinx_dsp.cc
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// At a high level, it works as follows:
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// (1) Starting from a DSP48E1 cell that (a) has the Z multiplexer
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// (controlled by OPMODE[6:4]) set to zero and (b) doesn't already
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// use the 'PCOUT' port
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// (2.1) Match another DSP48E1 cell that (a) does not have the CREG enabled,
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// (b) has its Z multiplexer output set to the 'C' port, which is
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// driven by the 'P' output of the previous DSP cell, and (c) has its
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// 'PCIN' port unused
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// (2.2) Same as (2.1) but with the 'C' port driven by the 'P' output of the
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// previous DSP cell right-shifted by 17 bits
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// (3) For this subequent DSP48E1 match (i.e. PCOUT -> PCIN cascade exists)
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// if (a) the previous DSP48E1 uses either the A2REG or A1REG, (b) this
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// DSP48 does not use A2REG nor A1REG, (c) this DSP48E1 does not already
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// have an ACOUT -> ACIN cascade, (d) the previous DSP does not already
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// use its ACOUT port, then examine if an ACOUT -> ACIN cascade
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// opportunity exists by matching for a $dff-with-optional-clock-enable-
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// or-reset and checking that the 'D' input of this register is the same
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// as the 'A' input of the previous DSP
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// (4) Same as (3) but for BCOUT -> BCIN cascade
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// (5) Recursively go to (2.1) until no more matches possible, keeping track
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// of the longest possible chain found
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// (6) The longest chain is then divided into chunks of no more than
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// MAX_DSP_CASCADE in length (to prevent long cascades that exceed the
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// height of a DSP column) with each DSP in each chunk being rewritten
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// to use [ABP]COUT -> [ABP]CIN cascading as appropriate
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// Notes:
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// - Currently, [AB]COUT -> [AB]COUT cascades (3 or 4) are only considered
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// if a PCOUT -> PCIN cascade is (2.1 or 2.2) first identified; this need
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// not be the case --- [AB] cascades can exist independently of a P cascade
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// (though all three cascades must come from the same DSP). This situation
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// is not handled currently.
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// - In addition, [AB]COUT -> [AB]COUT cascades (3 or 4) are currently
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// conservative in that they examine the situation where (a) the previous
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// DSP has [AB]2REG or [AB]1REG enabled, (b) that the downstream DSP has no
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// registers enabled, and (c) that there exists only one additional register
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// between the upstream and downstream DSPs. This can certainly be relaxed
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// to identify situations ranging from (i) neither DSP uses any registers,
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// to (ii) upstream DSP has 2 registers, downstream DSP has 2 registers, and
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// there exists a further 2 registers between them. This remains a TODO
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// item.
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pattern xilinx_dsp_cascade
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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udata <vector<std::tuple<Cell*,int,int,int>>> chain longest_chain
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state <Cell*> next
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state <SigBit> clock
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state <int> AREG BREG
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// Variables used for subpatterns
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state <SigSpec> argQ argD
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff
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code
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#define MAX_DSP_CASCADE 20
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endcode
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// (1) Starting from a DSP48* cell that (a) has the Z multiplexer
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// (controlled by OPMODE[3:2] for DSP48A*, by OPMODE[6:4] for DSP48E1)
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// set to zero and (b) doesn't already use the 'PCOUT' port
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match first
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select (first->type.in(\DSP48A, \DSP48A1) && port(first, \OPMODE, Const(0, 8)).extract(2,2) == Const::from_string("00")) || (first->type.in(\DSP48E1) && port(first, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("000"))
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select nusers(port(first, \PCOUT, SigSpec())) <= 1
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endmatch
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// (6) The longest chain is then divided into chunks of no more than
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// MAX_DSP_CASCADE in length (to prevent long cascades that exceed the
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// height of a DSP column) with each DSP in each chunk being rewritten
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// to use [ABP]COUT -> [ABP]CIN cascading as appropriate
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code
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longest_chain.clear();
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chain.emplace_back(first, -1, -1, -1);
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subpattern(tail);
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finally
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chain.pop_back();
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log_assert(chain.empty());
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if (GetSize(longest_chain) > 1) {
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Cell *dsp = std::get<0>(longest_chain.front());
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Cell *dsp_pcin;
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int P, AREG, BREG;
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for (int i = 1; i < GetSize(longest_chain); i++) {
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std::tie(dsp_pcin,P,AREG,BREG) = longest_chain[i];
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if (i % MAX_DSP_CASCADE > 0) {
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if (P >= 0) {
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Wire *cascade = module->addWire(NEW_ID, 48);
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dsp_pcin->setPort(ID(C), Const(0, 48));
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dsp_pcin->setPort(ID(PCIN), cascade);
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dsp->setPort(ID(PCOUT), cascade);
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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SigSpec opmode = port(dsp_pcin, \OPMODE, Const(0, 7));
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if (dsp->type.in(\DSP48A, \DSP48A1)) {
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log_assert(P == 0);
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opmode[3] = State::S0;
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opmode[2] = State::S1;
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}
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else if (dsp->type.in(\DSP48E1)) {
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if (P == 17)
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opmode[6] = State::S1;
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else if (P == 0)
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opmode[6] = State::S0;
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else log_abort();
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opmode[5] = State::S0;
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opmode[4] = State::S1;
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}
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dsp_pcin->setPort(\OPMODE, opmode);
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log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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}
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if (AREG >= 0) {
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Wire *cascade = module->addWire(NEW_ID, 30);
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dsp_pcin->setPort(ID(A), Const(0, 30));
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dsp_pcin->setPort(ID(ACIN), cascade);
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dsp->setPort(ID(ACOUT), cascade);
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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if (dsp->type.in(\DSP48E1))
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dsp->setParam(ID(ACASCREG), AREG);
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dsp_pcin->setParam(ID(A_INPUT), Const("CASCADE"));
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log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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}
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if (BREG >= 0) {
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Wire *cascade = module->addWire(NEW_ID, 18);
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if (dsp->type.in(\DSP48A, \DSP48A1)) {
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// According to UG389 p9 [https://www.xilinx.com/support/documentation/user_guides/ug389.pdf]
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// "The DSP48A1 component uses this input when cascading
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// BCOUT from an adjacent DSP48A1 slice. The tools then
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// translate BCOUT cascading to the dedicated BCIN input
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// and set the B_INPUT attribute for implementation."
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dsp_pcin->setPort(ID(B), cascade);
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}
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else {
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dsp_pcin->setPort(ID(B), Const(0, 18));
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dsp_pcin->setPort(ID(BCIN), cascade);
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}
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dsp->setPort(ID(BCOUT), cascade);
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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if (dsp->type.in(\DSP48E1)) {
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dsp->setParam(ID(BCASCREG), BREG);
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// According to UG389 p13 [https://www.xilinx.com/support/documentation/user_guides/ug389.pdf]
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// "The attribute is only used by place and route tools and
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// is not necessary for the users to set for synthesis. The
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// attribute is determined by the connection to the B port
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// of the DSP48A1 slice. If the B port is connected to the
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// BCOUT of another DSP48A1 slice, then the tools automatically
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// set the attribute to 'CASCADE', otherwise it is set to
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// 'DIRECT'".
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dsp_pcin->setParam(ID(B_INPUT), Const("CASCADE"));
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}
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log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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}
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}
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else {
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log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
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}
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dsp = dsp_pcin;
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}
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accept;
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}
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endcode
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// ------------------------------------------------------------------
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subpattern tail
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arg first
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arg next
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// (2.1) Match another DSP48* cell that (a) does not have the CREG enabled,
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// (b) has its Z multiplexer output set to the 'C' port, which is
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// driven by the 'P' output of the previous DSP cell, and (c) has its
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// 'PCIN' port unused
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match nextP
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select !nextP->type.in(\DSP48E1) || !param(nextP, \CREG).as_bool()
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select (nextP->type.in(\DSP48A, \DSP48A1) && port(nextP, \OPMODE, Const(0, 8)).extract(2,2) == Const::from_string("11")) || (nextP->type.in(\DSP48E1) && port(nextP, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011"))
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select nusers(port(nextP, \C, SigSpec())) > 1
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select nusers(port(nextP, \PCIN, SigSpec())) == 0
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index <SigBit> port(nextP, \C)[0] === port(std::get<0>(chain.back()), \P)[0]
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semioptional
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endmatch
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// (2.2) For DSP48E1 only, same as (2.1) but with the 'C' port driven
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// by the 'P' output of the previous DSP cell right-shifted by 17 bits
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match nextP_shift17
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if !nextP
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select nextP_shift17->type.in(\DSP48E1)
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select !param(nextP_shift17, \CREG).as_bool()
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select port(nextP_shift17, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(nextP_shift17, \C, SigSpec())) > 1
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select nusers(port(nextP_shift17, \PCIN, SigSpec())) == 0
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index <SigBit> port(nextP_shift17, \C)[0] === port(std::get<0>(chain.back()), \P)[17]
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semioptional
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endmatch
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code next
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next = nextP;
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if (!nextP)
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next = nextP_shift17;
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if (next) {
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if (next->type != first->type)
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reject;
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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}
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endcode
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// (3) For this subequent DSP48E1 match (i.e. PCOUT -> PCIN cascade exists)
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// if (a) this DSP48E1 does not already have an ACOUT -> ACIN cascade,
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// (b) the previous DSP does not already use its ACOUT port, then
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// examine if an ACOUT -> ACIN cascade opportunity exists if
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// (i) A ports are identical, or (ii) separated by a
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// $dff-with-optional-clock-enable-or-reset and checking that the 'D' input
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// of this register is the same as the 'A' input of the previous DSP
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// TODO: Check for two levels of flops, instead of just one
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code argQ clock AREG
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AREG = -1;
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if (next && next->type.in(\DSP48E1)) {
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Cell *prev = std::get<0>(chain.back());
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if (param(next, \A_INPUT).decode_string() == "DIRECT" &&
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port(next, \ACIN, SigSpec()).is_fully_zero() &&
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nusers(port(prev, \ACOUT, SigSpec())) <= 1) {
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if (param(prev, \AREG) == 0) {
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if (port(prev, \A) == port(next, \A))
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AREG = 0;
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}
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else {
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argQ = unextend(port(next, \A));
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clock = port(prev, \CLK);
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subpattern(in_dffe);
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if (dff) {
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if (!dff->type.in($sdff, $sdffe) && port(prev, \RSTA, State::S0) != State::S0)
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goto reject_AREG;
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if (dff->type.in($sdff, $sdffe) && (port(dff, \SRST) != port(prev, \RSTA, State::S0) || !param(dff, \SRST_POLARITY).as_bool()))
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goto reject_AREG;
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IdString CEA;
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if (param(prev, \AREG) == 1)
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CEA = \CEA2;
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else if (param(prev, \AREG) == 2)
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CEA = \CEA1;
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else log_abort();
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if (!dff->type.in($dffe, $sdffe) && port(prev, CEA, State::S0) != State::S1)
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goto reject_AREG;
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if (dff->type.in($dffe, $sdffe) && (port(dff, \EN) != port(prev, CEA, State::S0) || !param(dff, \EN_POLARITY).as_bool()))
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goto reject_AREG;
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if (dffD == unextend(port(prev, \A)))
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AREG = 1;
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}
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}
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}
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reject_AREG: ;
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}
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endcode
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// (4) Same as (3) but for BCOUT -> BCIN cascade
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code argQ clock BREG
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BREG = -1;
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if (next) {
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Cell *prev = std::get<0>(chain.back());
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if ((next->type != \DSP48E1 || param(next, \B_INPUT).decode_string() == "DIRECT") &&
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port(next, \BCIN, SigSpec()).is_fully_zero() &&
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nusers(port(prev, \BCOUT, SigSpec())) <= 1) {
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if ((next->type.in(\DSP48A, \DSP48A1) && param(prev, \B0REG) == 0 && param(prev, \B1REG) == 0) ||
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(next->type.in(\DSP48E1) && param(prev, \BREG) == 0)) {
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if (port(prev, \B) == port(next, \B))
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BREG = 0;
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}
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else {
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argQ = unextend(port(next, \B));
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clock = port(prev, \CLK);
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subpattern(in_dffe);
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if (dff) {
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if (!dff->type.in($sdff, $sdffe) && port(prev, \RSTB, State::S0) != State::S0)
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goto reject_BREG;
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if (dff->type.in($sdff, $sdffe) && (port(dff, \SRST) != port(prev, \RSTB, State::S0) || !param(dff, \SRST_POLARITY).as_bool()))
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goto reject_BREG;
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IdString CEB;
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if (next->type.in(\DSP48A, \DSP48A1))
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CEB = \CEB;
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else if (next->type.in(\DSP48E1)) {
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if (param(prev, \BREG) == 1)
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CEB = \CEB2;
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else if (param(prev, \BREG) == 2)
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CEB = \CEB1;
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else log_abort();
|
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}
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else log_abort();
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if (!dff->type.in($dffe, $sdffe) && port(prev, CEB, State::S0) != State::S1)
|
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goto reject_BREG;
|
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if (dff->type.in($dffe, $sdffe) && (port(dff, \EN) != port(prev, CEB, State::S0) || !param(dff, \EN_POLARITY).as_bool()))
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goto reject_BREG;
|
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if (dffD == unextend(port(prev, \B))) {
|
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if (next->type.in(\DSP48A, \DSP48A1) && param(prev, \B0REG) != 0)
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goto reject_BREG;
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BREG = 1;
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}
|
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}
|
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}
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}
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reject_BREG: ;
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}
|
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endcode
|
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|
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// (5) Recursively go to (2.1) until no more matches possible, recording the
|
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// longest possible chain
|
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code
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if (next) {
|
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chain.emplace_back(next, nextP_shift17 ? 17 : nextP ? 0 : -1, AREG, BREG);
|
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|
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SigSpec sigC = unextend(port(next, \C));
|
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|
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if (nextP_shift17) {
|
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if (GetSize(sigC)+17 <= GetSize(port(std::get<0>(chain.back()), \P)) &&
|
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port(std::get<0>(chain.back()), \P).extract(17, GetSize(sigC)) != sigC)
|
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subpattern(tail);
|
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}
|
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else {
|
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if (GetSize(sigC) <= GetSize(port(std::get<0>(chain.back()), \P)) &&
|
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port(std::get<0>(chain.back()), \P).extract(0, GetSize(sigC)) != sigC)
|
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subpattern(tail);
|
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|
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}
|
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} else {
|
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if (GetSize(chain) > GetSize(longest_chain))
|
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longest_chain = chain;
|
||||
}
|
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finally
|
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if (next)
|
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chain.pop_back();
|
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endcode
|
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|
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// #######################
|
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|
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// Subpattern for matching against input registers, based on knowledge of the
|
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// 'Q' input.
|
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subpattern in_dffe
|
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arg argQ clock
|
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|
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code
|
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dff = nullptr;
|
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if (argQ.empty())
|
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reject;
|
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for (const auto &c : argQ.chunks()) {
|
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// Abandon matches when 'Q' is a constant
|
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if (!c.wire)
|
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reject;
|
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// Abandon matches when 'Q' has the keep attribute set
|
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if (c.wire->get_bool_attribute(\keep))
|
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reject;
|
||||
// Abandon matches when 'Q' has a non-zero init attribute set
|
||||
// (not supported by DSP48E1)
|
||||
Const init = c.wire->attributes.at(\init, Const());
|
||||
if (!init.empty())
|
||||
for (auto b : init.extract(c.offset, c.width))
|
||||
if (b != State::Sx && b != State::S0)
|
||||
reject;
|
||||
}
|
||||
endcode
|
||||
|
||||
match ff
|
||||
select ff->type.in($dff, $dffe, $sdff, $sdffe)
|
||||
// DSP48E1 does not support clock inversion
|
||||
select param(ff, \CLK_POLARITY).as_bool()
|
||||
|
||||
// Check that reset value, if present, is fully 0.
|
||||
filter ff->type.in($dff, $dffe) || param(ff, \SRST_VALUE).is_fully_zero()
|
||||
|
||||
slice offset GetSize(port(ff, \D))
|
||||
index <SigBit> port(ff, \Q)[offset] === argQ[0]
|
||||
|
||||
// Check that the rest of argQ is present
|
||||
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
|
||||
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
|
||||
|
||||
filter clock == SigBit() || port(ff, \CLK)[0] == clock
|
||||
endmatch
|
||||
|
||||
code argQ
|
||||
SigSpec Q = port(ff, \Q);
|
||||
dff = ff;
|
||||
dffclock = port(ff, \CLK);
|
||||
dffD = argQ;
|
||||
SigSpec D = port(ff, \D);
|
||||
argQ = Q;
|
||||
dffD.replace(argQ, D);
|
||||
endcode
|
||||
Loading…
Add table
Add a link
Reference in a new issue