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https://github.com/YosysHQ/yosys
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pmgen: Move passes out of pmgen folder
- Techlib pmgens are now in relevant techlibs/*. - `peepopt` pmgens are now in passes/opt. - `test_pmgen` is still in passes/pmgen. - Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location, as well as the `#include`s. - Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the top level Makefile. - Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir $@))`.
This commit is contained in:
Krystine Sherwin
parent
18a7c00382
commit
0ec5f1b756
31 changed files with 71 additions and 77 deletions
490
techlibs/xilinx/xilinx_dsp.pmg
Normal file
490
techlibs/xilinx/xilinx_dsp.pmg
Normal file
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@ -0,0 +1,490 @@
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// This file describes the main pattern matcher setup (of three total) that
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// forms the `xilinx_dsp` pass described in xilinx_dsp.cc
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// At a high level, it works as follows:
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// ( 1) Starting from a DSP48E1 cell
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// ( 2) Match the driver of the 'A' input to a possible $sdffe cell (ADREG)
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// If ADREG matched, treat 'A' input as input of ADREG
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// ( 3) Match the driver of the 'A' and 'D' inputs for a possible $add cell
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// (pre-adder)
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// ( 4) If pre-adder was present, find match 'A' input for A2REG
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// If pre-adder was not present, move ADREG to A2REG
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// If A2REG, then match 'A' input for A1REG
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// ( 5) Match 'B' input for B2REG
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// If B2REG, then match 'B' input for B1REG
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// ( 6) Match 'D' input for DREG
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// ( 7) Match 'P' output that exclusively drives an MREG
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// ( 8) Match 'P' output that exclusively drives one of two inputs to an $add
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// cell (post-adder).
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// The other input to the adder is assumed to come in from the 'C' input
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// (note: 'P' -> 'C' connections that exist for accumulators are
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// recognised in xilinx_dsp.cc).
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// ( 9) Match 'P' output that exclusively drives a PREG
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// (10) If post-adder and PREG both present, match for a $mux cell driving
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// the 'C' input, where one of the $mux's inputs is the PREG output.
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// This indicates an accumulator situation, and one where a $mux exists
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// to override the accumulated value:
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// +--------------------------------+
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// | ____ |
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// +--| \ |
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// |$mux|-+ |
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// 'C' ---|____/ | |
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// | /-------\ +----+ |
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// +----+ +-| post- |___|PREG|---+ 'P'
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// |MREG|------ | adder | +----+
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// +----+ \-------/
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// (11) If PREG present, match for a greater-than-or-equal $ge cell attached
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// to the 'P' output where it is compared to a constant that is a
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// power-of-2: e.g. `assign overflow = (PREG >= 2**40);`
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// In this scenario, the pattern detector functionality of a DSP48E1 can
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// to implement this function
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// Notes:
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// - The intention of this pattern matcher is for it to be compatible with
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// DSP48E1 cells inferred from multiply operations by Yosys, as well as for
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// user instantiations that may already contain the cells being packed...
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// (though the latter is currently untested)
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// - Since the $sdffe pattern is used
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// for each *REG match, it has been factored out into two subpatterns:
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// in_dffe and out_dffe located at the bottom of this file.
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// - Matching for pattern detector features is currently incomplete. For
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// example, matching for underflow as well as overflow detection is
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// possible, as would auto-reset, enabling saturated arithmetic, detecting
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// custom patterns, etc.
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pattern xilinx_dsp_pack
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state <SigBit> clock
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state <SigSpec> sigA sigB sigC sigD sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <Cell*> ffAD ffA1 ffA2
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state <Cell*> ffB1 ffB2
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state <Cell*> ffD ffM ffP
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// Variables used for subpatterns
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state <SigSpec> argQ argD
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff
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// (1) Starting from a DSP48E1 cell
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match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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code sigA sigB sigC sigD sigM clock
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auto unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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sigA = unextend(port(dsp, \A));
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sigB = unextend(port(dsp, \B));
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sigC = port(dsp, \C, SigSpec());
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sigD = port(dsp, \D, SigSpec());
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SigSpec P = port(dsp, \P);
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if (param(dsp, \USE_MULT).decode_string() == "MULTIPLY") {
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// Only care about those bits that are used
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int i;
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for (i = GetSize(P)-1; i >= 0; i--)
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if (nusers(P[i]) > 1)
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break;
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i++;
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log_assert(nusers(P.extract_end(i)) <= 1);
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// This sigM could have no users if downstream sinks (e.g. $add) is
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// narrower than $mul result, for example
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if (i == 0)
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reject;
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sigM = P.extract(0, i);
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}
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else
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sigM = P;
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clock = port(dsp, \CLK, SigBit());
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endcode
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// (2) Match the driver of the 'A' input to a possible $sdffe cell (ADREG)
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// If matched, treat 'A' input as input of ADREG
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code argQ ffAD sigA clock
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if (param(dsp, \ADREG).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffAD = dff;
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clock = dffclock;
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sigA = dffD;
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}
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}
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endcode
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// (3) Match the driver of the 'A' and 'D' inputs for a possible $add cell
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// (pre-adder)
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match preAdd
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if sigD.empty() || sigD.is_fully_zero()
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// Ensure that preAdder not already used
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if param(dsp, \USE_DPORT).decode_string() == "FALSE"
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if port(dsp, \INMODE, Const(0, 5)).is_fully_zero()
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select preAdd->type.in($add)
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// Output has to be 25 bits or less
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select GetSize(port(preAdd, \Y)) <= 25
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select nusers(port(preAdd, \Y)) == 2
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choice <IdString> AB {\A, \B}
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// A port has to be 30 bits or less
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select GetSize(port(preAdd, AB)) <= 30
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define <IdString> BA (AB == \A ? \B : \A)
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// D port has to be 25 bits or less
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select GetSize(port(preAdd, BA)) <= 25
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index <SigSpec> port(preAdd, \Y) === sigA
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optional
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endmatch
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code sigA sigD
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if (preAdd) {
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sigA = port(preAdd, \A);
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sigD = port(preAdd, \B);
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}
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endcode
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// (4) If pre-adder was present, find match 'A' input for A2REG
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// If pre-adder was not present, move ADREG to A2REG
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// Then match 'A' input for A1REG
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code argQ ffAD sigA clock ffA2 ffA1
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// Only search for ffA2 if there was a pre-adder
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// (otherwise ffA2 would have been matched as ffAD)
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if (preAdd) {
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if (param(dsp, \AREG).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffA2 = dff;
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clock = dffclock;
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sigA = dffD;
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}
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}
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}
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// And if there wasn't a pre-adder,
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// move AD register to A
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else if (ffAD) {
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log_assert(!ffA2);
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std::swap(ffA2, ffAD);
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}
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// Now attempt to match A1
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if (ffA2) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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if (dff->type != ffA2->type)
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goto ffA1_end;
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if (dff->type.in($sdff, $sdffe, $sdffce)) {
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if (param(dff, \SRST_POLARITY) != param(ffA2, \SRST_POLARITY))
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goto ffA1_end;
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if (port(dff, \SRST) != port(ffA2, \SRST))
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goto ffA1_end;
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}
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if (dff->type.in($dffe, $sdffe, $sdffce)) {
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if (param(dff, \EN_POLARITY) != param(ffA2, \EN_POLARITY))
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goto ffA1_end;
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if (port(dff, \EN) != port(ffA2, \EN))
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goto ffA1_end;
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}
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ffA1 = dff;
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clock = dffclock;
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sigA = dffD;
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ffA1_end: ;
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}
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}
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endcode
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// (5) Match 'B' input for B2REG
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// If B2REG, then match 'B' input for B1REG
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code argQ ffB2 sigB clock ffB1
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if (param(dsp, \BREG).as_int() == 0) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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ffB2 = dff;
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clock = dffclock;
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sigB = dffD;
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// Now attempt to match B1
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if (ffB2) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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if (dff->type != ffB2->type)
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goto ffB1_end;
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if (dff->type.in($sdff, $sdffe, $sdffce)) {
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if (param(dff, \SRST_POLARITY) != param(ffB2, \SRST_POLARITY))
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goto ffB1_end;
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if (port(dff, \SRST) != port(ffB2, \SRST))
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goto ffB1_end;
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}
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if (dff->type.in($dffe, $sdffe, $sdffce)) {
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if (param(dff, \EN_POLARITY) != param(ffB2, \EN_POLARITY))
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goto ffB1_end;
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if (port(dff, \EN) != port(ffB2, \EN))
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goto ffB1_end;
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}
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ffB1 = dff;
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clock = dffclock;
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sigB = dffD;
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ffB1_end: ;
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}
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}
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}
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}
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endcode
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// (6) Match 'D' input for DREG
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code argQ ffD sigD clock
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if (param(dsp, \DREG).as_int() == 0) {
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argQ = sigD;
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subpattern(in_dffe);
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if (dff) {
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ffD = dff;
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clock = dffclock;
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sigD = dffD;
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}
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}
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endcode
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// (7) Match 'P' output that exclusively drives an MREG
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code argD ffM sigM sigP clock
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if (param(dsp, \MREG).as_int() == 0 && nusers(sigM) == 2) {
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argD = sigM;
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subpattern(out_dffe);
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if (dff) {
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ffM = dff;
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clock = dffclock;
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sigM = dffQ;
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}
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}
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sigP = sigM;
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endcode
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// (8) Match 'P' output that exclusively drives one of two inputs to an $add
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// cell (post-adder).
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// The other input to the adder is assumed to come in from the 'C' input
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// (note: 'P' -> 'C' connections that exist for accumulators are
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// recognised in xilinx_dsp.cc).
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match postAdd
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// Ensure that Z mux is not already used
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if port(dsp, \OPMODE, SigSpec(0, 7)).extract(4,3).is_fully_zero()
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select postAdd->type.in($add)
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select GetSize(port(postAdd, \Y)) <= 48
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choice <IdString> AB {\A, \B}
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select nusers(port(postAdd, AB)) == 2
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index <SigBit> port(postAdd, AB)[0] === sigP[0]
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filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
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filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP
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// Check that remainder of AB is a sign- or zero-extension
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filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP)) || port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(State::S0, GetSize(port(postAdd, AB))-GetSize(sigP))
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set postAddAB AB
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optional
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endmatch
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code sigC sigP
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if (postAdd) {
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sigC = port(postAdd, postAddAB == \A ? \B : \A);
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sigP = port(postAdd, \Y);
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}
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endcode
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// (9) Match 'P' output that exclusively drives a PREG
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code argD ffP sigP clock
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if (param(dsp, \PREG).as_int() == 0) {
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if (nusers(sigP) == 2) {
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argD = sigP;
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subpattern(out_dffe);
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if (dff) {
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ffP = dff;
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clock = dffclock;
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sigP = dffQ;
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}
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}
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}
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endcode
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// (10) If post-adder and PREG both present, match for a $mux cell driving
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// the 'C' input, where one of the $mux's inputs is the PREG output.
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// This indicates an accumulator situation, and one where a $mux exists
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// to override the accumulated value:
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// +--------------------------------+
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// | ____ |
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// +--| \ |
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// |$mux|-+ |
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// 'C' ---|____/ | |
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// | /-------\ +----+ |
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// +----+ +-| post- |___|PREG|---+ 'P'
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// |MREG|------ | adder | +----+
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// +----+ \-------/
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match postAddMux
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if postAdd
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if ffP
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select postAddMux->type.in($mux)
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select nusers(port(postAddMux, \Y)) == 2
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(postAddMux, AB) === sigP
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index <SigSpec> port(postAddMux, \Y) === sigC
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set postAddMuxAB AB
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optional
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endmatch
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code sigC
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if (postAddMux)
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sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
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endcode
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// (11) If PREG present, match for a greater-than-or-equal $ge cell attached to
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// the 'P' output where it is compared to a constant that is a power-of-2:
|
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// e.g. `assign overflow = (PREG >= 2**40);`
|
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// In this scenario, the pattern detector functionality of a DSP48E1 can
|
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// to implement this function
|
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match overflow
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if ffP
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if param(dsp, \USE_PATTERN_DETECT).decode_string() == "NO_PATDET"
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select overflow->type.in($ge)
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select GetSize(port(overflow, \Y)) <= 48
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select port(overflow, \B).is_fully_const()
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define <Const> B port(overflow, \B).as_const()
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select std::count(B.begin(), B.end(), State::S1) == 1
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index <SigSpec> port(overflow, \A) === sigP
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optional
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endmatch
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code
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accept;
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endcode
|
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|
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// #######################
|
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|
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// Subpattern for matching against input registers, based on knowledge of the
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// 'Q' input.
|
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subpattern in_dffe
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arg argQ clock
|
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|
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code
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dff = nullptr;
|
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if (argQ.empty())
|
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reject;
|
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for (const auto &c : argQ.chunks()) {
|
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// Abandon matches when 'Q' is a constant
|
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if (!c.wire)
|
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reject;
|
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// Abandon matches when 'Q' has the keep attribute set
|
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if (c.wire->get_bool_attribute(\keep))
|
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reject;
|
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// Abandon matches when 'Q' has a non-zero init attribute set
|
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// (not supported by DSP48E1)
|
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Const init = c.wire->attributes.at(\init, Const());
|
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if (!init.empty())
|
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for (auto b : init.extract(c.offset, c.width))
|
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if (b != State::Sx && b != State::S0)
|
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reject;
|
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}
|
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endcode
|
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|
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match ff
|
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select ff->type.in($dff, $dffe, $sdff, $sdffe)
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// DSP48E1 does not support clock inversion
|
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select param(ff, \CLK_POLARITY).as_bool()
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|
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// Check that reset value, if present, is fully 0.
|
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filter ff->type.in($dff, $dffe) || param(ff, \SRST_VALUE).is_fully_zero()
|
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|
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slice offset GetSize(port(ff, \D))
|
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index <SigBit> port(ff, \Q)[offset] === argQ[0]
|
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|
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// Check that the rest of argQ is present
|
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filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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|
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filter clock == SigBit() || port(ff, \CLK)[0] == clock
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endmatch
|
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|
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code argQ
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SigSpec Q = port(ff, \Q);
|
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dff = ff;
|
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dffclock = port(ff, \CLK);
|
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dffD = argQ;
|
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SigSpec D = port(ff, \D);
|
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argQ = Q;
|
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dffD.replace(argQ, D);
|
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endcode
|
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|
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// #######################
|
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|
||||
// Subpattern for matching against output registers, based on knowledge of the
|
||||
// 'D' input.
|
||||
// At a high level:
|
||||
// (1) Starting from an optional $mux cell that implements clock enable
|
||||
// semantics --- one where the given 'D' argument (partially or fully)
|
||||
// drives one of its two inputs
|
||||
// (2) Starting from, or continuing onto, another optional $mux cell that
|
||||
// implements synchronous reset semantics --- one where the given 'D'
|
||||
// argument (or the clock enable $mux output) drives one of its two inputs
|
||||
// and where the other input is fully zero
|
||||
// (3) Match for a $dff cell (whose 'D' input is the 'D' argument, or the
|
||||
// output of the previous clock enable or reset $mux cells)
|
||||
subpattern out_dffe
|
||||
arg argD argQ clock
|
||||
|
||||
code
|
||||
dff = nullptr;
|
||||
for (auto c : argD.chunks())
|
||||
// Abandon matches when 'D' has the keep attribute set
|
||||
if (c.wire->get_bool_attribute(\keep))
|
||||
reject;
|
||||
endcode
|
||||
|
||||
match ff
|
||||
select ff->type.in($dff, $dffe, $sdff, $sdffe)
|
||||
// DSP48E1 does not support clock inversion
|
||||
select param(ff, \CLK_POLARITY).as_bool()
|
||||
|
||||
slice offset GetSize(port(ff, \D))
|
||||
index <SigBit> port(ff, \D)[offset] === argD[0]
|
||||
|
||||
// Check that the rest of argD is present
|
||||
filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
|
||||
filter port(ff, \D).extract(offset, GetSize(argD)) == argD
|
||||
|
||||
filter clock == SigBit() || port(ff, \CLK)[0] == clock
|
||||
endmatch
|
||||
|
||||
code argQ
|
||||
SigSpec D = port(ff, \D);
|
||||
SigSpec Q = port(ff, \Q);
|
||||
argQ = argD;
|
||||
argQ.replace(D, Q);
|
||||
|
||||
// Abandon matches when 'Q' has a non-zero init attribute set
|
||||
// (not supported by DSP48E1)
|
||||
for (auto c : argQ.chunks()) {
|
||||
Const init = c.wire->attributes.at(\init, Const());
|
||||
if (!init.empty())
|
||||
for (auto b : init.extract(c.offset, c.width))
|
||||
if (b != State::Sx && b != State::S0)
|
||||
reject;
|
||||
}
|
||||
|
||||
dff = ff;
|
||||
dffQ = argQ;
|
||||
dffclock = port(ff, \CLK);
|
||||
endcode
|
||||
Loading…
Add table
Add a link
Reference in a new issue