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pmgen: Move passes out of pmgen folder
- Techlib pmgens are now in relevant techlibs/*. - `peepopt` pmgens are now in passes/opt. - `test_pmgen` is still in passes/pmgen. - Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location, as well as the `#include`s. - Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the top level Makefile. - Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir $@))`.
This commit is contained in:
Krystine Sherwin
parent
18a7c00382
commit
0ec5f1b756
31 changed files with 71 additions and 77 deletions
168
techlibs/microchip/microchip_dsp_CREG.pmg
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168
techlibs/microchip/microchip_dsp_CREG.pmg
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// ISC License
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//
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// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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//
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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// This file describes the second of three pattern matcher setups that
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// forms the `microchip_dsp` pass described in microchip_dsp.cc
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// At a high level, it works as follows:
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// (1) Starting from a DSP cell that (a) doesn't have a CREG already,
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// and (b) uses the 'C' port
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// (2) Match the driver of the 'C' input to a possible $dff cell (CREG)
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// (attached to at most two $mux cells that implement clock-enable or
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// reset functionality, using a subpattern discussed below)
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// Notes:
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// - Running CREG packing after microchip_dsp_pack is necessary since there is no
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// guarantee that the cell ordering corresponds to the "expected" case (i.e.
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// the order in which they appear in the source) thus the possiblity existed
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// where a register got packed as a CREG into a downstream DSP, while it should
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// have otherwise been a PREG of an upstream DSP that had not been visited.
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// yet.
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// - The reason this is separated out from the microchip_dsp.pmg file is
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// for efficiency --- each *.pmg file creates a class of the same basename,
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// which when constructed, creates a custom database tailored to the
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// pattern(s) contained within. Since the pattern in this file must be
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// executed after the pattern contained in microchip_dsp.pmg, it is necessary
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// to reconstruct this database. Separating the two patterns into
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// independent files causes two smaller, more specific, databases.
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pattern microchip_dsp_packC
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigC sigP
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state <Cell*> ffC
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// Variables used for subpatterns
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state <SigSpec> argQ argD
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff
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// (1) Starting from a DSP cell that (a) doesn't have a CREG already,
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// and (b) uses the 'C' port
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match dsp
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select dsp->type.in(\MACC_PA)
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select port(dsp, \C_BYPASS, SigSpec()).is_fully_ones()
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select nusers(port(dsp, \C, SigSpec())) > 1
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endmatch
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code sigC sigP clock
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//helper function to remove unused bits
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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sigC = unextend(port(dsp, \C, SigSpec()));
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SigSpec P = port(dsp, \P);
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// Only care about those bits that are used
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int i;
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for (i = GetSize(P)-1; i >= 0; i--)
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if (nusers(P[i]) > 1)
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break;
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i++;
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log_assert(nusers(P.extract_end(i)) <= 1);
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sigP = P.extract(0, i);
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clock = port(dsp, \CLK, SigBit());
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endcode
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// (2) Match the driver of the 'C' input to a possible $dff cell (CREG)
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// (attached to at most two $mux cells that implement clock-enable or
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// reset functionality, using the in_dffe subpattern)
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code argQ ffC sigC clock
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argQ = sigC;
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subpattern(in_dffe);
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if (dff) {
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ffC = dff;
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clock = dffclock;
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sigC = dffD;
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}
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endcode
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code
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if (ffC)
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accept;
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endcode
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// #######################
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// Subpattern for matching against input registers, based on knowledge of the
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// 'Q' input.
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subpattern in_dffe
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arg argQ clock
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code
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dff = nullptr;
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if (argQ.empty())
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reject;
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for (const auto &c : argQ.chunks()) {
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// Abandon matches when 'Q' is a constant
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if (!c.wire)
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reject;
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// Abandon matches when 'Q' has the keep attribute set
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if (c.wire->get_bool_attribute(\keep))
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reject;
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// Abandon matches when 'Q' has a non-zero init attribute set
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Const init = c.wire->attributes.at(\init, Const());
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if (!init.empty())
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for (auto b : init.extract(c.offset, c.width))
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if (b != State::Sx && b != State::S0)
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reject;
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}
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endcode
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match ff
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select ff->type.in($dff, $dffe, $sdff, $sdffe, $adff, $adffe)
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// does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \Q)[offset] === argQ[0]
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// Check that the rest of argQ is present
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filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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filter clock == SigBit() || port(ff, \CLK)[0] == clock
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endmatch
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code argQ
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// Check that reset value, if present, is fully 0.
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bool noResetFlop = ff->type.in($dff, $dffe);
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bool srstZero = ff->type.in($sdff, $sdffe) && param(ff, \SRST_VALUE).is_fully_zero();
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bool arstZero = ff->type.in($adff, $adffe) && param(ff, \ARST_VALUE).is_fully_zero();
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bool resetLegal = noResetFlop || srstZero || arstZero;
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if (resetLegal)
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{
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SigSpec Q = port(ff, \Q);
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dff = ff;
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dffclock = port(ff, \CLK);
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dffD = argQ;
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SigSpec D = port(ff, \D);
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argQ = Q;
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dffD.replace(argQ, D);
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}
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endcode
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