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https://github.com/YosysHQ/yosys
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pmgen: Move passes out of pmgen folder
- Techlib pmgens are now in relevant techlibs/*. - `peepopt` pmgens are now in passes/opt. - `test_pmgen` is still in passes/pmgen. - Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location, as well as the `#include`s. - Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the top level Makefile. - Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir $@))`.
This commit is contained in:
Krystine Sherwin
parent
18a7c00382
commit
0ec5f1b756
31 changed files with 71 additions and 77 deletions
1
passes/opt/.gitignore
vendored
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1
passes/opt/.gitignore
vendored
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@ -0,0 +1 @@
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/peepopt*_pm.h
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@ -22,4 +22,18 @@ OBJS += passes/opt/opt_lut_ins.o
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OBJS += passes/opt/opt_ffinv.o
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OBJS += passes/opt/pmux2shiftx.o
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OBJS += passes/opt/muxpack.o
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OBJS += passes/opt/peepopt.o
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GENFILES += passes/opt/peepopt_pm.h
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passes/opt/peepopt.o: passes/opt/peepopt_pm.h
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$(eval $(call add_extra_objs,passes/opt/peepopt_pm.h))
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PEEPOPT_PATTERN = passes/opt/peepopt_shiftmul_right.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_shiftmul_left.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_shiftadd.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_muldiv.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_formal_clockgateff.pmg
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passes/opt/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
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$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)
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endif
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114
passes/opt/peepopt.cc
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114
passes/opt/peepopt.cc
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@ -0,0 +1,114 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool did_something;
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// scratchpad configurations for pmgen
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int shiftadd_max_ratio;
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#include "passes/opt/peepopt_pm.h"
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struct PeepoptPass : public Pass {
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PeepoptPass() : Pass("peepopt", "collection of peephole optimizers") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" peepopt [options] [selection]\n");
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log("\n");
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log("This pass applies a collection of peephole optimizers to the current design.\n");
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log("\n");
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log("This pass employs the following rules by default:\n");
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log("\n");
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log(" * muldiv - Replace (A*B)/B with A\n");
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log("\n");
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log(" * shiftmul - Replace A>>(B*C) with A'>>(B<<K) where C and K are constants\n");
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log(" and A' is derived from A by appropriately inserting padding\n");
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log(" into the signal. (right variant)\n");
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log("\n");
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log(" Analogously, replace A<<(B*C) with appropriate selection of\n");
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log(" output bits from A<<(B<<K). (left variant)\n");
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log("\n");
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log(" * shiftadd - Replace A>>(B+D) with (A'>>D)>>(B) where D is constant and\n");
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log(" A' is derived from A by padding or cutting inaccessible bits.\n");
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log(" Scratchpad: 'peepopt.shiftadd.max_data_multiple' (default: 2)\n");
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log(" limits the amount of padding to a multiple of the data, \n");
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log(" to avoid high resource usage from large temporary MUX trees.\n");
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log("\n");
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log("If -formalclk is specified it instead employs the following rules:\n");
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log("\n");
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log(" * clockgateff - Replace latch based clock gating patterns with a flip-flop\n");
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log(" based pattern to prevent combinational paths from the\n");
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log(" output to the enable input after running clk2fflogic.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n");
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bool formalclk = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-formalclk") {
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formalclk = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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// limit the padding from shiftadd to a multiple of the input data
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// during techmap it creates (#data + #padding) * log(shift) $_MUX_ cells
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// 2x implies there is a constant shift larger than the input-data which should be extremely rare
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shiftadd_max_ratio = design->scratchpad_get_int("peepopt.shiftadd.max_data_multiple", 2);
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for (auto module : design->selected_modules())
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{
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did_something = true;
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while (did_something)
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{
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did_something = false;
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peepopt_pm pm(module);
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pm.setup(module->selected_cells());
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if (formalclk) {
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pm.run_formal_clockgateff();
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} else {
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pm.run_shiftadd();
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pm.run_shiftmul_right();
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pm.run_shiftmul_left();
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pm.run_muldiv();
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}
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}
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}
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}
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} PeepoptPass;
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PRIVATE_NAMESPACE_END
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59
passes/opt/peepopt_formal_clockgateff.pmg
Normal file
59
passes/opt/peepopt_formal_clockgateff.pmg
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@ -0,0 +1,59 @@
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pattern formal_clockgateff
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// Detects the most common clock gating pattern using a latch and replaces it
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// with a functionally equivalent pattern based on a flip-flop. The latch
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// based pattern has a combinational path from the enable input to output after
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// clk2fflogic, but this is a stable loop and the flip-flop based pattern does
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// not exhibit this.
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//
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// This optimization is suitable for formal to prevent false comb loops, but
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// should not be used for synthesis where the latch is an intentional choice
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//
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// Latch style:
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// always @* if (!clk_i) latched_en = en;
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// assign gated_clk_o = latched_en & clk_i;
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//
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// Flip-flop style:
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// always @(posedge clk) flopped_en <= en;
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// assign gated_clk_o = flopped_en & clk_i;
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state <SigSpec> clk en latched_en gated_clk
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state <IdString> latched_en_port_name
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match latch
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select latch->type == $dlatch
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select param(latch, \WIDTH) == 1
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select param(latch, \EN_POLARITY).as_bool() == false
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set clk port(latch, \EN)
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set en port(latch, \D)
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set latched_en port(latch, \Q)
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endmatch
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match and_gate
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select and_gate->type.in($and, $logic_and)
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select param(and_gate, \A_WIDTH) == 1
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select param(and_gate, \B_WIDTH) == 1
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select param(and_gate, \Y_WIDTH) == 1
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choice <IdString> clk_port {\A, \B}
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define <IdString> latch_port {clk_port == \A ? \B : \A}
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index <SigSpec> port(and_gate, clk_port) === clk
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index <SigSpec> port(and_gate, latch_port) === latched_en
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set gated_clk port(and_gate, \Y)
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set latched_en_port_name latch_port
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endmatch
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code
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log("replacing clock gate pattern in %s with ff: latch=%s, and=%s\n",
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log_id(module), log_id(latch), log_id(and_gate));
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// Add a flip-flop and rewire the AND gate to use the output of this flop
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// instead of the latch. We don't delete the latch in case its output is
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// used to drive other nodes. If it isn't, it will be trivially removed by
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// clean
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SigSpec flopped_en = module->addWire(NEW_ID);
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module->addDff(NEW_ID, clk, en, flopped_en, true, latch->get_src_attribute());
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and_gate->setPort(latched_en_port_name, flopped_en);
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did_something = true;
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accept;
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endcode
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39
passes/opt/peepopt_muldiv.pmg
Normal file
39
passes/opt/peepopt_muldiv.pmg
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@ -0,0 +1,39 @@
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pattern muldiv
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state <SigSpec> t x y
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state <bool> is_signed
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match mul
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select mul->type == $mul
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select GetSize(port(mul, \A)) + GetSize(port(mul, \B)) <= GetSize(port(mul, \Y))
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endmatch
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code t x y is_signed
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t = port(mul, \Y);
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x = port(mul, \A);
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y = port(mul, \B);
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is_signed = param(mul, \A_SIGNED).as_bool();
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branch;
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std::swap(x, y);
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endcode
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match div
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select div->type.in($div)
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index <SigSpec> port(div, \A) === t
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index <SigSpec> port(div, \B) === x
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filter param(div, \A_SIGNED).as_bool() == is_signed
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endmatch
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code
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SigSpec div_y = port(div, \Y);
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SigSpec val_y = y;
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if (GetSize(div_y) != GetSize(val_y))
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val_y.extend_u0(GetSize(div_y), param(div, \A_SIGNED).as_bool());
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did_something = true;
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log("muldiv pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
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module->connect(div_y, val_y);
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autoremove(div);
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accept;
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endcode
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151
passes/opt/peepopt_shiftadd.pmg
Normal file
151
passes/opt/peepopt_shiftadd.pmg
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@ -0,0 +1,151 @@
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pattern shiftadd
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//
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// Transforms add/sub+shift pairs that result from expressions such as data[s*W +C +:W2]
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// specifically something like: out[W2-1:0] = data >> (s*W +C)
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// will be transformed into: out[W2-1:0] = (data >> C) >> (s*W)
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// this can then be optimized using peepopt_shiftmul_right.pmg
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//
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match shift
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select shift->type.in($shift, $shiftx, $shr)
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filter !port(shift, \B).empty()
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endmatch
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// the right shift amount
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state <SigSpec> shift_amount
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// log2 scale factor in interpreting of shift_amount
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// due to zero padding on the shift cell's B port
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state <int> log2scale
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// zeros at the MSB position make it unsigned
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state <bool> msb_zeros
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code shift_amount log2scale msb_zeros
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shift_amount = port(shift, \B);
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log2scale = 0;
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while (shift_amount[0] == State::S0) {
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shift_amount.remove(0);
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if (shift_amount.empty()) reject;
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log2scale++;
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}
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msb_zeros = 0;
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while (shift_amount.bits().back() == State::S0) {
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msb_zeros = true;
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shift_amount.remove(GetSize(shift_amount) - 1);
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if (shift_amount.empty()) reject;
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}
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endcode
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state <bool> var_signed
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state <SigSpec> var_signal
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// offset: signed constant value c in data[var+c +:W1] (constant shift-right amount)
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state <int> offset
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match add
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// either data[var+c +:W1] or data[var-c +:W1]
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select add->type.in($add, $sub)
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index <SigSpec> port(add, \Y) === shift_amount
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// one must be constant, the other is variable
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choice <IdString> constport {\A, \B}
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select !port(add, constport).empty()
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select port(add, constport).is_fully_const()
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define <IdString> varport (constport == \A ? \B : \A)
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// only optimize for constants up to a fixed width. this prevents cases
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// with a blowup in internal term size and prevents larger constants being
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// casted to int incorrectly
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select (GetSize(port(add, constport)) <= 24)
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// if a value of var is able to wrap the output, the transformation might give wrong results
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// an addition/substraction can at most flip one more bit than the largest operand (the carry bit)
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// as long as the output can show this bit, no wrap should occur (assuming all signed-ness make sense)
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select ( GetSize(port(add, \Y)) > max(GetSize(port(add, \A)), GetSize(port(add, \B))) )
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define <bool> varport_A (varport == \A)
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define <bool> is_sub add->type.in($sub)
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define <bool> constport_signed param(add, !varport_A ? \A_SIGNED : \B_SIGNED).as_bool()
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define <bool> varport_signed param(add, varport_A ? \A_SIGNED : \B_SIGNED).as_bool();
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define <bool> const_negative (constport_signed && (port(add, constport).bits().back() == State::S1))
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define <bool> offset_negative ((is_sub && varport_A) ^ const_negative)
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// checking some value boundaries as well:
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// data[...-c +:W1] is fine for any signed var (pad at LSB, all data still accessible)
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// unsigned shift may underflow (eg var-3 with var<3) -> cannot be converted
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// data[...+c +:W1] is only fine for +var(add) and var unsigned
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// (+c cuts lower C bits, making them inaccessible, a signed var could try to access them)
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// either its an add or the variable port is A (it must be positive)
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select (add->type.in($add) || varport == \A)
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// -> data[var+c +:W1] (with var signed) is illegal
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filter !(!offset_negative && varport_signed)
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// -> data >> (var-c) (with var unsigned) is illegal
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filter !(offset_negative && !varport_signed)
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// state-variables are assigned at the end only:
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// shift the log2scale offset in-front of add to get true value: (var+c)<<N -> (var<<N)+(c<<N)
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set offset ( (port(add, constport).as_int(constport_signed) << log2scale) * ( (is_sub && varport_A) ? -1 : 1 ) )
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set var_signed varport_signed
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set var_signal add->getPort(varport)
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endmatch
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code
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{
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// positive constant offset with a signed variable (index) cannot be handled
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// the above filter should get rid of this case but 'offset' is calculated differently
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// due to limitations of state-variables in pmgen
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// it should only differ if previous passes create invalid data
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log_assert(!(offset>0 && var_signed));
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SigSpec old_a = port(shift, \A); // data
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std::string location = shift->get_src_attribute();
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if(shiftadd_max_ratio>0 && offset<0 && -offset*shiftadd_max_ratio > old_a.size()) {
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log_warning("at %s: candiate for shiftadd optimization (shifting '%s' by '%s - %d' bits) "
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"was ignored to avoid high resource usage, see help peepopt\n",
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location.c_str(), log_signal(old_a), log_signal(var_signal), -offset);
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reject;
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}
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did_something = true;
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log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \
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log_id(module), log_id(shift), log_id(add), offset);
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SigSpec new_a;
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if(offset<0) {
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// data >> (...-c) transformed to {data, c'X} >> (...)
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SigSpec padding( (shift->type.in($shiftx) ? State::Sx : State::S0), -offset );
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new_a.append(padding);
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new_a.append(old_a);
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} else {
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// data >> (...+c) transformed to data[MAX:c] >> (...)
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if(offset < GetSize(old_a)) { // some signal bits left?
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new_a.append(old_a.extract_end(offset));
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} else {
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// warn user in case data is empty (no bits left)
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if (location.empty())
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location = shift->name.str();
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if(shift->type.in($shiftx))
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log_warning("at %s: result of indexed part-selection is always constant (selecting from '%s' with index '%s + %d')\n", \
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location.c_str(), log_signal(old_a), log_signal(var_signal), offset);
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else
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log_warning("at %s: result of shift operation is always constant (shifting '%s' by '%s + %d' bits)\n", \
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location.c_str(), log_signal(old_a), log_signal(var_signal), offset);
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}
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}
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SigSpec new_b = {var_signal, SigSpec(State::S0, log2scale)};
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if (msb_zeros || !var_signed)
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new_b.append(State::S0);
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shift->setPort(\A, new_a);
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shift->setParam(\A_WIDTH, GetSize(new_a));
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shift->setPort(\B, new_b);
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shift->setParam(\B_WIDTH, GetSize(new_b));
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blacklist(add);
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accept;
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}
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endcode
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160
passes/opt/peepopt_shiftmul_left.pmg
Normal file
160
passes/opt/peepopt_shiftmul_left.pmg
Normal file
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@ -0,0 +1,160 @@
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pattern shiftmul_left
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//
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// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
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//
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||||
|
||||
match shift
|
||||
select shift->type.in($shift, $shiftx, $shl)
|
||||
select shift->type.in($shl) || param(shift, \B_SIGNED).as_bool()
|
||||
filter !port(shift, \B).empty()
|
||||
endmatch
|
||||
|
||||
match neg
|
||||
if shift->type.in($shift, $shiftx)
|
||||
select neg->type == $neg
|
||||
index <SigSpec> port(neg, \Y) === port(shift, \B)
|
||||
filter !port(shift, \A).empty()
|
||||
endmatch
|
||||
|
||||
// the left shift amount
|
||||
state <SigSpec> shift_amount
|
||||
// log2 scale factor in interpreting of shift_amount
|
||||
// due to zero padding on the shift cell's B port
|
||||
state <int> log2scale
|
||||
|
||||
code shift_amount log2scale
|
||||
if (neg) {
|
||||
// case of `$shift`, `$shiftx`
|
||||
shift_amount = port(neg, \A);
|
||||
if (!param(neg, \A_SIGNED).as_bool())
|
||||
shift_amount.append(State::S0);
|
||||
} else {
|
||||
// case of `$shl`
|
||||
shift_amount = port(shift, \B);
|
||||
if (!param(shift, \B_SIGNED).as_bool())
|
||||
shift_amount.append(State::S0);
|
||||
}
|
||||
|
||||
// at this point shift_amount is signed, make
|
||||
// sure we can never go negative
|
||||
if (shift_amount.bits().back() != State::S0)
|
||||
reject;
|
||||
|
||||
while (shift_amount.bits().back() == State::S0) {
|
||||
shift_amount.remove(GetSize(shift_amount) - 1);
|
||||
if (shift_amount.empty()) reject;
|
||||
}
|
||||
|
||||
log2scale = 0;
|
||||
while (shift_amount[0] == State::S0) {
|
||||
shift_amount.remove(0);
|
||||
if (shift_amount.empty()) reject;
|
||||
log2scale++;
|
||||
}
|
||||
|
||||
if (GetSize(shift_amount) > 20)
|
||||
reject;
|
||||
endcode
|
||||
|
||||
state <SigSpec> mul_din
|
||||
state <Const> mul_const
|
||||
|
||||
match mul
|
||||
select mul->type.in($mul)
|
||||
index <SigSpec> port(mul, \Y) === shift_amount
|
||||
filter !param(mul, \A_SIGNED).as_bool()
|
||||
|
||||
choice <IdString> constport {\A, \B}
|
||||
filter port(mul, constport).is_fully_const()
|
||||
|
||||
define <IdString> varport (constport == \A ? \B : \A)
|
||||
set mul_const SigSpec({port(mul, constport), SigSpec(State::S0, log2scale)}).as_const()
|
||||
// get mul_din unmapped (so no `port()` shorthand)
|
||||
// because we will be using it to set the \A port
|
||||
// on the shift cell, and we want to stay close
|
||||
// to the original design
|
||||
set mul_din mul->getPort(varport)
|
||||
endmatch
|
||||
|
||||
code
|
||||
{
|
||||
if (mul_const.empty() || GetSize(mul_const) > 20)
|
||||
reject;
|
||||
|
||||
// make sure there's no overlap in the signal
|
||||
// selections by the shiftmul pattern
|
||||
if (GetSize(port(shift, \A)) > mul_const.as_int())
|
||||
reject;
|
||||
|
||||
int factor_bits = ceil_log2(mul_const.as_int());
|
||||
// make sure the multiplication never wraps around
|
||||
if (GetSize(shift_amount) < factor_bits + GetSize(mul_din))
|
||||
reject;
|
||||
|
||||
if (neg) {
|
||||
// make sure the negation never wraps around
|
||||
if (GetSize(port(shift, \B)) < factor_bits + GetSize(mul_din)
|
||||
+ log2scale + 1)
|
||||
reject;
|
||||
}
|
||||
|
||||
did_something = true;
|
||||
log("left shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
|
||||
|
||||
int const_factor = mul_const.as_int();
|
||||
int new_const_factor = 1 << factor_bits;
|
||||
SigSpec padding(State::Sm, new_const_factor-const_factor);
|
||||
SigSpec old_y = port(shift, \Y), new_y;
|
||||
int trunc = 0;
|
||||
|
||||
if (GetSize(old_y) % const_factor != 0) {
|
||||
trunc = const_factor - GetSize(old_y) % const_factor;
|
||||
old_y.append(SigSpec(State::Sm, trunc));
|
||||
}
|
||||
|
||||
for (int i = 0; i*const_factor < GetSize(old_y); i++) {
|
||||
SigSpec slice = old_y.extract(i*const_factor, const_factor);
|
||||
new_y.append(slice);
|
||||
new_y.append(padding);
|
||||
}
|
||||
|
||||
if (trunc > 0)
|
||||
new_y.remove(GetSize(new_y)-trunc, trunc);
|
||||
|
||||
{
|
||||
// Now replace occurences of Sm in new_y with bits
|
||||
// of a dummy wire
|
||||
int padbits = 0;
|
||||
for (auto bit : new_y)
|
||||
if (bit == SigBit(State::Sm))
|
||||
padbits++;
|
||||
|
||||
SigSpec padwire = module->addWire(NEW_ID, padbits);
|
||||
|
||||
for (int i = new_y.size() - 1; i >= 0; i--)
|
||||
if (new_y[i] == SigBit(State::Sm)) {
|
||||
new_y[i] = padwire.bits().back();
|
||||
padwire.remove(padwire.size() - 1);
|
||||
}
|
||||
}
|
||||
|
||||
SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
|
||||
|
||||
shift->setPort(\Y, new_y);
|
||||
shift->setParam(\Y_WIDTH, GetSize(new_y));
|
||||
if (shift->type == $shl) {
|
||||
if (param(shift, \B_SIGNED).as_bool())
|
||||
new_b.append(State::S0);
|
||||
shift->setPort(\B, new_b);
|
||||
shift->setParam(\B_WIDTH, GetSize(new_b));
|
||||
} else {
|
||||
SigSpec b_neg = module->addWire(NEW_ID, GetSize(new_b) + 1);
|
||||
module->addNeg(NEW_ID, new_b, b_neg);
|
||||
shift->setPort(\B, b_neg);
|
||||
shift->setParam(\B_WIDTH, GetSize(b_neg));
|
||||
}
|
||||
|
||||
blacklist(shift);
|
||||
accept;
|
||||
}
|
||||
endcode
|
||||
108
passes/opt/peepopt_shiftmul_right.pmg
Normal file
108
passes/opt/peepopt_shiftmul_right.pmg
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
pattern shiftmul_right
|
||||
//
|
||||
// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
|
||||
//
|
||||
|
||||
match shift
|
||||
select shift->type.in($shift, $shiftx, $shr)
|
||||
filter !port(shift, \B).empty()
|
||||
endmatch
|
||||
|
||||
// the right shift amount
|
||||
state <SigSpec> shift_amount
|
||||
// log2 scale factor in interpreting of shift_amount
|
||||
// due to zero padding on the shift cell's B port
|
||||
state <int> log2scale
|
||||
|
||||
code shift_amount log2scale
|
||||
shift_amount = port(shift, \B);
|
||||
if (shift->type.in($shr) || !param(shift, \B_SIGNED).as_bool())
|
||||
shift_amount.append(State::S0);
|
||||
|
||||
// at this point shift_amount is signed, make
|
||||
// sure we can never go negative
|
||||
if (shift_amount.bits().back() != State::S0)
|
||||
reject;
|
||||
|
||||
while (shift_amount.bits().back() == State::S0) {
|
||||
shift_amount.remove(GetSize(shift_amount) - 1);
|
||||
if (shift_amount.empty()) reject;
|
||||
}
|
||||
|
||||
log2scale = 0;
|
||||
while (shift_amount[0] == State::S0) {
|
||||
shift_amount.remove(0);
|
||||
if (shift_amount.empty()) reject;
|
||||
log2scale++;
|
||||
}
|
||||
|
||||
if (GetSize(shift_amount) > 20)
|
||||
reject;
|
||||
endcode
|
||||
|
||||
state <SigSpec> mul_din
|
||||
state <Const> mul_const
|
||||
|
||||
match mul
|
||||
select mul->type.in($mul)
|
||||
index <SigSpec> port(mul, \Y) === shift_amount
|
||||
filter !param(mul, \A_SIGNED).as_bool()
|
||||
|
||||
choice <IdString> constport {\A, \B}
|
||||
filter port(mul, constport).is_fully_const()
|
||||
|
||||
define <IdString> varport (constport == \A ? \B : \A)
|
||||
set mul_const SigSpec({port(mul, constport), SigSpec(State::S0, log2scale)}).as_const()
|
||||
// get mul_din unmapped (so no `port()` shorthand)
|
||||
// because we will be using it to set the \A port
|
||||
// on the shift cell, and we want to stay close
|
||||
// to the original design
|
||||
set mul_din mul->getPort(varport)
|
||||
endmatch
|
||||
|
||||
code
|
||||
{
|
||||
if (mul_const.empty() || GetSize(mul_const) > 20)
|
||||
reject;
|
||||
|
||||
// make sure there's no overlap in the signal
|
||||
// selections by the shiftmul pattern
|
||||
if (GetSize(port(shift, \Y)) > mul_const.as_int())
|
||||
reject;
|
||||
|
||||
int factor_bits = ceil_log2(mul_const.as_int());
|
||||
// make sure the multiplication never wraps around
|
||||
if (GetSize(shift_amount) + log2scale < factor_bits + GetSize(mul_din))
|
||||
reject;
|
||||
|
||||
did_something = true;
|
||||
log("right shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
|
||||
|
||||
int const_factor = mul_const.as_int();
|
||||
int new_const_factor = 1 << factor_bits;
|
||||
SigSpec padding(State::Sx, new_const_factor-const_factor);
|
||||
SigSpec old_a = port(shift, \A), new_a;
|
||||
|
||||
for (int i = 0; i*const_factor < GetSize(old_a); i++) {
|
||||
if ((i+1)*const_factor < GetSize(old_a)) {
|
||||
SigSpec slice = old_a.extract(i*const_factor, const_factor);
|
||||
new_a.append(slice);
|
||||
new_a.append(padding);
|
||||
} else {
|
||||
new_a.append(old_a.extract_end(i*const_factor));
|
||||
}
|
||||
}
|
||||
|
||||
SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
|
||||
if (param(shift, \B_SIGNED).as_bool())
|
||||
new_b.append(State::S0);
|
||||
|
||||
shift->setPort(\A, new_a);
|
||||
shift->setParam(\A_WIDTH, GetSize(new_a));
|
||||
shift->setPort(\B, new_b);
|
||||
shift->setParam(\B_WIDTH, GetSize(new_b));
|
||||
|
||||
blacklist(shift);
|
||||
accept;
|
||||
}
|
||||
endcode
|
||||
Loading…
Add table
Add a link
Reference in a new issue