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Add test
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21
tests/various/split_shiftx.ys
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21
tests/various/split_shiftx.ys
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read_verilog -icells split_shiftx.v
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split_shiftx
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cd split_shiftx_test01
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select -assert-count 3 t:$shiftx
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select -assert-count 0 t: t:$shiftx %n %i
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cd split_shiftx_test02
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select -assert-count 1 t:$shiftx
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select -assert-count 1 t:$macc
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select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
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cd split_shiftx_test03
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select -assert-count 1 t:$shiftx
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select -assert-count 1 t:$macc
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select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
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cd split_shiftx_test04
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select -assert-count 1 t:$shiftx
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select -assert-count 1 t:$macc
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select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
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