mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

Fix simple_abc9/generate test with 1'bx at MSB

Browse source
This commit is contained in:
Eddie Hung 2019-06-20 19:37:03 -07:00
parent ad36eb24c0
commit 0e97e6a00d
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
passes/techmap/abc9.cc
View file

@ -492,7 +492,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
if (w->port_output) { if (w->port_output) {
RTLIL::Wire *wire = module->wire(w->name); RTLIL::Wire *wire = module->wire(w->name);
log_assert(wire); log_assert(wire);
for (int i = 0; i < GetSize(wire); i++) for (int i = 0; i < GetSize(w); i++)
output_bits.insert({wire, i}); output_bits.insert({wire, i});
} }
} }