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address greptile
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3a1f4e00ca
commit
0e906c1d3e
1 changed files with 8 additions and 4 deletions
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@ -127,7 +127,7 @@ vector<string> verific_incdirs, verific_libdirs, verific_libexts;
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vector<string> verific_force_ram_signals;
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// SILIMATE: stamp the force_ram attribute onto the registered signals.
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static void apply_force_ram_signals()
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static void apply_force_ram_signals(const char *work)
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{
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for (auto &entry : verific_force_ram_signals) {
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// Validation
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@ -140,7 +140,11 @@ static void apply_force_ram_signals()
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std::string module_name = entry.substr(0, dot);
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std::string signal_name = entry.substr(dot + 1);
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// Find module and signal from the design
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VeriModule *veri_module = veri_file::GetModule(module_name.c_str());
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VeriModule *veri_module = veri_file::GetModule(module_name.c_str(), 1, work);
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if (!veri_module) {
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log_warning("-force-ram: module '%s' not found.\n", module_name.c_str());
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continue;
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}
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VeriScope *scope = veri_module ? veri_module->GetScope() : nullptr;
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VeriIdDef *id = scope ? scope->FindLocal(signal_name.c_str()) : nullptr;
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if (!id) {
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@ -3067,7 +3071,7 @@ void restore_blackbox_msg_state()
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void import_all(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED)
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{
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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apply_force_ram_signals(); // SILIMATE
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apply_force_ram_signals(work); // SILIMATE
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#endif
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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save_blackbox_msg_state();
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@ -3139,7 +3143,7 @@ std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist
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(void)top;
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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apply_force_ram_signals(); // SILIMATE
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apply_force_ram_signals(work); // SILIMATE
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#endif
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#ifdef VERIFIC_VHDL_SUPPORT
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