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https://github.com/YosysHQ/yosys
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Auto-generate .box/.lut files from specify blocks
This commit is contained in:
Eddie Hung
parent
3d6603792d
commit
0e7c55e2a7
8 changed files with 268 additions and 466 deletions
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@ -23,9 +23,6 @@
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#include "kernel/utils.h"
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#include "kernel/celltypes.h"
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#define ABC9_FLOPS_BASE_ID 8000
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#define ABC9_DELAY_BASE_ID 9000
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -269,7 +266,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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if (abc9_flop && !dff)
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continue;
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if ((inst_module && inst_module->attributes.count("\\abc9_box_id")) || abc9_flop) {
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if ((inst_module && inst_module->get_bool_attribute("\\abc9_box")) || abc9_flop) {
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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// Make carry in the last PI, and carry out the last PO
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@ -350,7 +347,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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log_assert(cell);
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RTLIL::Module* box_module = design->module(cell->type);
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if (!box_module || (!box_module->attributes.count("\\abc9_box_id") && !box_module->get_bool_attribute("\\abc9_flop")))
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if (!box_module || (!box_module->get_bool_attribute("\\abc9_box") && !box_module->get_bool_attribute("\\abc9_flop")))
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continue;
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cell->attributes["\\abc9_box_seq"] = box_count++;
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@ -431,7 +428,6 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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void prep_delays(RTLIL::Design *design)
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{
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std::set<int> delays;
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pool<Module*> flops;
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std::vector<Cell*> cells;
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dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
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@ -459,7 +455,7 @@ void prep_delays(RTLIL::Design *design)
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continue; // because all flop required times
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// will be captured in the flop box
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}
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if (inst_module->attributes.count(ID(abc9_box_id)))
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if (inst_module->attributes.count(ID(abc9_box)))
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continue;
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cells.emplace_back(cell);
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}
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@ -481,13 +477,11 @@ void prep_delays(RTLIL::Design *design)
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continue;
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if (it->second.flags == 0) {
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int delay = it->second.as_int();
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delays.insert(delay);
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requireds.emplace_back(delay);
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}
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else
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for (const auto &tok : split_tokens(it->second.decode_string())) {
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int delay = atoi(tok.c_str());
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delays.insert(delay);
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requireds.push_back(delay);
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}
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}
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@ -516,12 +510,13 @@ void prep_delays(RTLIL::Design *design)
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}
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}
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int flops_id = ABC9_FLOPS_BASE_ID;
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int abc9_box_id = design->scratchpad_get_int("abc9_ops.box_id");
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std::stringstream ss;
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for (auto flop_module : flops) {
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int num_inputs = 0, num_outputs = 0;
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for (auto port_name : flop_module->ports) {
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auto wire = flop_module->wire(port_name);
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log_assert(GetSize(wire) == 1);
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if (wire->port_input) num_inputs++;
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if (wire->port_output) num_outputs++;
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}
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@ -529,11 +524,27 @@ void prep_delays(RTLIL::Design *design)
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auto r = flop_module->attributes.insert(ID(abc9_box_id));
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if (r.second)
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r.first->second = flops_id++;
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r.first->second = ++abc9_box_id;
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ss << log_id(flop_module) << " " << r.first->second.as_int();
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ss << " 1 " << num_inputs+1 << " " << num_outputs << std::endl;
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ss << " " << (flop_module->get_bool_attribute(ID::whitebox) ? "1" : "0");
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ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
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ss << "#";
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bool first = true;
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for (auto port_name : flop_module->ports) {
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auto wire = flop_module->wire(port_name);
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if (!wire->port_input)
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continue;
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if (first)
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first = false;
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else
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ss << " ";
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ss << log_id(wire);
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}
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ss << " abc9_ff.Q" << std::endl;
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first = true;
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for (auto port_name : flop_module->ports) {
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auto wire = flop_module->wire(port_name);
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if (!wire->port_input)
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@ -548,13 +559,7 @@ void prep_delays(RTLIL::Design *design)
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ss << " 0" << std::endl << std::endl;
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}
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design->scratchpad_set_string("abc9_ops.box_library.flops", ss.str());
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ss.str("");
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for (const int d : delays) {
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ss << "$__ABC9_DELAY@" << d << " " << ABC9_DELAY_BASE_ID + d << " 0 1 1" << std::endl;
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ss << d << std::endl;
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}
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design->scratchpad_set_string("abc9_ops.box_library.delays", ss.str());
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design->scratchpad_set_int("abc9_ops.box_id", abc9_box_id);
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}
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void prep_lut(RTLIL::Design *design, int maxlut)
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@ -610,22 +615,93 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
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ofs.close();
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}
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void prep_box(RTLIL::Design *design, const std::string &src)
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void prep_box(RTLIL::Design *design)
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{
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std::stringstream ss;
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ss << design->scratchpad_get_string("abc9_ops.box_library.flops", ss.str());
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// Since ABC can only accept one box file, we have to copy
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// over the existing box file
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if (src != "(null)") {
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std::ifstream ifs(src);
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log_assert(ifs.is_open());
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ss << ifs.rdbuf() << std::endl;
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ifs.close();
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int abc9_box_id = design->scratchpad_get_int("abc9_ops.box_id");
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for (auto module : design->modules()) {
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auto it = module->attributes.find(ID(abc9_box));
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if (it == module->attributes.end())
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continue;
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module->attributes.erase(it);
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log_assert(!module->attributes.count(ID(abc9_box_id)));
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dict<std::pair<SigBit,SigBit>, std::string> table;
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std::vector<SigBit> inputs;
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std::vector<SigBit> outputs;
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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if (wire->port_input)
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for (int i = 0; i < GetSize(wire); i++)
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inputs.emplace_back(wire, i);
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if (wire->port_output)
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for (int i = 0; i < GetSize(wire); i++)
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outputs.emplace_back(wire, i);
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}
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for (auto cell : module->cells()) {
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if (cell->type != ID($specify2))
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continue;
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auto src = cell->getPort(ID(SRC));
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auto dst = cell->getPort(ID(DST));
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for (const auto &c : src.chunks())
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if (!c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
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for (const auto &c : dst.chunks())
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if (!c.wire->port_output)
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
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int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
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int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
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int max = std::max(rise_max,fall_max);
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for (auto s : src)
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for (auto d : dst) {
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auto r = table.insert(std::make_pair(s,d));
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log_assert(r.second);
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r.first->second = std::to_string(max);
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}
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}
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auto r = module->attributes.insert(ID(abc9_box_id));
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log_assert(r.second);
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r.first->second = ++abc9_box_id;
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ss << log_id(module) << " " << abc9_box_id;
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ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
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ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
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bool first = true;
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ss << "#";
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for (const auto &i : inputs) {
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if (first)
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first = false;
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else
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ss << " ";
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if (GetSize(i.wire) == 1)
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ss << log_id(i.wire);
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else
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ss << log_id(i.wire) << "[" << i.offset << "]";
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}
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ss << std::endl;
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for (const auto &o : outputs) {
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first = true;
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for (const auto &i : inputs) {
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if (first)
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first = false;
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else
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ss << " ";
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ss << table.at(std::make_pair(i,o), "-");
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}
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ss << " # ";
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if (GetSize(o.wire) == 1)
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ss << log_id(o.wire);
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else
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ss << log_id(o.wire) << "[" << o.offset << "]";
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ss << std::endl;
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}
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ss << std::endl;
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}
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ss << design->scratchpad_get_string("abc9_ops.box_library.flops", ss.str());
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ss << design->scratchpad_get_string("abc9_ops.box_library.delays", ss.str());
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design->scratchpad_set_string("abc9_ops.box_library", ss.str());
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design->scratchpad_set_int("abc9_ops.box_id", abc9_box_id);
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}
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void write_box(RTLIL::Module *module, const std::string &dst) {
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@ -1049,14 +1125,15 @@ struct Abc9OpsPass : public Pass {
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log(" process the '$holes' module to support clock-enable functionality.\n");
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log("\n");
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log(" -prep_lut <maxlut>\n");
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log(" pre-compute the lut library.\n");
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log(" pre-compute the lut library by analysing all modules marked with\n");
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log(" (* abc9_lut=<area> *).\n");
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log("\n");
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log(" -write_lut <dst>\n");
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log(" write the pre-computed lut library to <dst>.\n");
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log("\n");
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log(" -prep_box <src>\n");
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log(" pre-compute the box library. copy the existing box file from <src> (skip\n");
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log(" if '(null)').\n");
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log(" -prep_box\n");
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log(" pre-compute the box library by analysing all modules marked with\n");
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log(" (* abc9_box *)\n");
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log("\n");
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log(" -write_box <dst>\n");
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log(" write the pre-computed box library to <dst>.\n");
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@ -1077,11 +1154,12 @@ struct Abc9OpsPass : public Pass {
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bool prep_dff_mode = false;
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bool prep_xaiger_mode = false;
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bool prep_lut_mode = false;
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bool prep_box_mode = false;
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bool reintegrate_mode = false;
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bool dff_mode = false;
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std::string write_lut_dst;
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int maxlut = 0;
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std::string prep_box_src, write_box_dst;
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std::string write_box_dst;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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@ -1119,9 +1197,8 @@ struct Abc9OpsPass : public Pass {
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rewrite_filename(write_lut_dst);
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continue;
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}
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if (arg == "-prep_box" && argidx+1 < args.size()) {
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prep_box_src = args[++argidx];
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rewrite_filename(prep_box_src);
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if (arg == "-prep_box") {
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prep_box_mode = true;
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continue;
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}
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if (arg == "-write_box" && argidx+1 < args.size()) {
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@ -1141,7 +1218,7 @@ struct Abc9OpsPass : public Pass {
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}
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extra_args(args, argidx, design);
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if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || !prep_box_src.empty() || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
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if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || prep_box_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
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log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
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if (dff_mode && !prep_xaiger_mode)
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@ -1153,8 +1230,8 @@ struct Abc9OpsPass : public Pass {
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prep_delays(design);
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if (prep_lut_mode)
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prep_lut(design, maxlut);
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if (!prep_box_src.empty())
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prep_box(design, prep_box_src);
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if (prep_box_mode)
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prep_box(design);
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for (auto mod : design->selected_modules()) {
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if (mod->get_bool_attribute("\\abc9_holes"))
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