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Use read_techlib where applicable

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This commit is contained in:
Miodrag Milanovic 2026-06-12 10:01:24 +02:00
parent cf316ad85e
commit 0dfbd13fe7
38 changed files with 64 additions and 64 deletions
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2
techlibs/quicklogic/CMakeLists.txt
View file

@ -63,7 +63,7 @@ yosys_pass(synth_quicklogic
ql_dsp_macc
ql_dsp_simd
ql_ioff
read_verilog
read_techlib
setundef
share
shregmap

4
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -198,7 +198,7 @@ struct SynthQuickLogicPass : public ScriptPass {
}
if (check_label("begin")) {
std::string read_simlibs = stringf("read_verilog -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path, lib_path, family);
std::string read_simlibs = stringf("read_techlib -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path, lib_path, family);
if (family == "qlf_k6n10f") {
read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path);
if (bramTypes)
@ -317,7 +317,7 @@ struct SynthQuickLogicPass : public ScriptPass {
if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
run("techmap -map " + lib_path + family + "/latches_map.v");
if (abc9) {
run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");
run("read_techlib -lib -specify -icells " + lib_path + family + "/abc9_model.v");
run("techmap -map " + lib_path + family + "/abc9_map.v");
run("abc9 -maxlut 4 -dff");
run("techmap -map " + lib_path + family + "/abc9_unmap.v");