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Use read_techlib where applicable
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38 changed files with 64 additions and 64 deletions
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@ -47,7 +47,7 @@ yosys_pass(synth_microchip
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opt_expr
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peepopt
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proc
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read_verilog
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read_techlib
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select
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setattr
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share
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@ -260,7 +260,7 @@ struct SynthMicrochipPass : public ScriptPass {
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if (check_label("begin")) {
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std::string read_args;
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read_args += " -lib -specify +/microchip/cells_sim.v";
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run("read_verilog" + read_args);
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run("read_techlib" + read_args);
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run(stringf("hierarchy -check %s", top_opt));
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}
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