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Use read_techlib where applicable
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cf316ad85e
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38 changed files with 64 additions and 64 deletions
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@ -22,7 +22,7 @@ yosys_pass(synth_intel_alm
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opt_expr
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peepopt
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proc
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read_verilog
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read_techlib
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share
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stat
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techmap
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@ -169,16 +169,16 @@ struct SynthIntelALMPass : public ScriptPass {
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if (check_label("begin")) {
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if (family_opt == "cyclonev")
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run(stringf("read_verilog -sv -lib +/intel_alm/%s/cells_sim.v", family_opt));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/misc_sim.v", family_opt));
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run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt));
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run(stringf("read_techlib -sv -lib +/intel_alm/%s/cells_sim.v", family_opt));
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run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt));
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run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt));
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run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt));
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run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt));
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run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/misc_sim.v", family_opt));
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run(stringf("read_techlib -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt));
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// Misc and common cells
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run("read_verilog -lib +/intel/common/altpll_bb.v");
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run("read_verilog -lib +/intel_alm/common/megafunction_bb.v");
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run("read_techlib -lib +/intel/common/altpll_bb.v");
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run("read_techlib -lib +/intel_alm/common/megafunction_bb.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
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}
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