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Use read_techlib where applicable

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This commit is contained in:
Miodrag Milanovic 2026-06-12 10:01:24 +02:00
parent cf316ad85e
commit 0dfbd13fe7
38 changed files with 64 additions and 64 deletions
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6
techlibs/intel/synth_intel.cc
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@ -188,11 +188,11 @@ struct SynthIntelPass : public ScriptPass {
{
if (check_label("begin")) {
if (check_label("family"))
run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt));
run(stringf("read_techlib -sv -lib +/intel/%s/cells_sim.v", family_opt));
// Misc and common cells
run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
run("read_techlib -sv -lib +/intel/common/m9k_bb.v");
run("read_techlib -sv -lib +/intel/common/altpll_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}