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Use read_techlib where applicable

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This commit is contained in:
Miodrag Milanovic 2026-06-12 10:01:24 +02:00
parent cf316ad85e
commit 0dfbd13fe7
38 changed files with 64 additions and 64 deletions
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2
techlibs/gowin/CMakeLists.txt
View file

@ -24,7 +24,7 @@ yosys_pass(synth_gowin
opt_lut_ins
peepopt
proc
read_verilog
read_techlib
setundef
share
simplemap

8
techlibs/gowin/synth_gowin.cc
View file

@ -257,8 +257,8 @@ struct SynthGowinPass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -specify -lib +/gowin/cells_sim.v");
run(stringf("read_verilog -specify -lib +/gowin/cells_xtra_%s.v", help_mode ? "<family>" : family));
run("read_techlib -specify -lib +/gowin/cells_sim.v");
run(stringf("read_techlib -specify -lib +/gowin/cells_xtra_%s.v", help_mode ? "<family>" : family));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
@ -362,12 +362,12 @@ struct SynthGowinPass : public ScriptPass
{
run("sort");
if (nowidelut && abc9) {
run("read_verilog -icells -lib -specify +/abc9_model.v");
run("read_techlib -icells -lib -specify +/abc9_model.v");
run("abc9 -maxlut 4 -W 500");
} else if (nowidelut && !abc9) {
run("abc -lut 4");
} else if (!nowidelut && abc9) {
run("read_verilog -icells -lib -specify +/abc9_model.v");
run("read_techlib -icells -lib -specify +/abc9_model.v");
run("abc9 -maxlut 8 -W 500");
} else if (!nowidelut && !abc9) {
run("abc -lut 4:8");