3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-25 18:20:37 +00:00

Use read_techlib where applicable

This commit is contained in:
Miodrag Milanovic 2026-06-12 10:01:24 +02:00
parent cf316ad85e
commit 0dfbd13fe7
38 changed files with 64 additions and 64 deletions

View file

@ -23,7 +23,7 @@ yosys_pass(synth_anlogic
opt
opt_expr
proc
read_verilog
read_techlib
simplemap
stat
synth

View file

@ -149,7 +149,7 @@ struct SynthAnlogicPass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v");
run("read_techlib -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}