mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-27 11:08:48 +00:00
Code Activity

Use read_techlib where applicable

Browse source
This commit is contained in:
Miodrag Milanovic 2026-06-12 10:01:24 +02:00
parent cf316ad85e
commit 0dfbd13fe7
38 changed files with 64 additions and 64 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/achronix/CMakeLists.txt
View file

@ -13,7 +13,7 @@ yosys_pass(synth_achronix
memory_map
opt
proc
read_verilog
read_techlib
setundef
stat
synth

2
techlibs/achronix/synth_achronix.cc
View file

@ -122,7 +122,7 @@ struct SynthAchronixPass : public ScriptPass {
{
if (check_label("begin"))
{
run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
run("read_techlib -sv -lib +/achronix/speedster22i/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}