mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-15 19:55:41 +00:00
Code Activity

Actual merge here

Browse source
This commit is contained in:
Akash Levy 2025-04-06 18:53:43 -07:00
parent 69ce16c4a0
commit 0dab4308a3
40 changed files with 720 additions and 279 deletions
Download patch file Download diff file Expand all files Collapse all files

4
docs/source/code_examples/extensions/my_cmd.cc
View file

@ -51,10 +51,10 @@ struct Test2Pass : public Pass {
Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
void execute(std::vector<std::string>, RTLIL::Design *design) override
{
if (design->selection_stack.back().empty())
if (design->selection().empty())
log_cmd_error("This command can't operator on an empty selection!\n");
RTLIL::Module *module = design->modules_.at("\\test");
RTLIL::Module *module = design->module("\\test");
RTLIL::SigSpec a(module->wire("\\a")), x(module->wire("\\x")), y(module->wire("\\y"));
log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"