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Sign extend port connections where necessary

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- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
This commit is contained in:
Zachary Snow 2020-12-18 12:59:08 -07:00
parent 40e35993af
commit 0d8e5d965f
5 changed files with 132 additions and 5 deletions
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8
passes/hierarchy/hierarchy.cc
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@ -1233,14 +1233,18 @@ struct HierarchyPass : public Pass {
{
int n = GetSize(conn.second) - GetSize(w);
if (!w->port_input && w->port_output)
module->connect(sig.extract(GetSize(w), n), Const(0, n));
{
RTLIL::SigSpec out = sig.extract(0, GetSize(w));
out.extend_u0(GetSize(sig), w->is_signed);
module->connect(sig.extract(GetSize(w), n), out.extract(GetSize(w), n));
}
sig.remove(GetSize(w), n);
}
else
{
int n = GetSize(w) - GetSize(conn.second);
if (w->port_input && !w->port_output)
sig.append(Const(0, n));
sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed);
else
sig.append(module->addWire(NEW_ID, n));
}