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https://github.com/YosysHQ/yosys
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Add support for A/B/C/D/AD reset
This commit is contained in:
Eddie Hung
parent
6a95ecd41d
commit
0d709d2bb5
2 changed files with 141 additions and 139 deletions
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@ -2,12 +2,13 @@ pattern xilinx_dsp
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state <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigffAmuxY sigB sigffBmuxY sigC sigffCmuxY sigD sigffDmuxY sigM sigP
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state <SigSpec> sigA sigffAcemuxY sigB sigffBcemuxY sigC sigffCcemuxY sigD sigffDcemuxY sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <bool> ffAcepol ffADcepol ffBcepol ffCcepol ffDcepol ffMcepol ffMrstpol ffPcepol ffPrstpol
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state <int> ffPoffset
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state <bool> ffAcepol ffADcepol ffBcepol ffCcepol ffDcepol ffMcepol ffPcepol
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state <bool> ffArstpol ffADrstpol ffBrstpol ffCrstpol ffDrstpol ffMrstpol ffPrstpol
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state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux ffM ffMcemux ffMrstmux ffP ffPcemux ffPrstmux
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state <Cell*> ffAD ffADcemux ffADrstmux ffA ffAcemux ffArstmux ffB ffBcemux ffBrstmux ffC ffCcemux ffCrstmux
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state <Cell*> ffD ffDcemux ffDrstmux ffM ffMcemux ffMrstmux ffP ffPcemux ffPrstmux
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// subpattern
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state <SigSpec> argQ argD
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@ -54,7 +55,7 @@ code unextend sigA sigB sigC sigD sigM
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sigM = P;
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endcode
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code argQ ffAD ffADmux ffADcepol sigA clock
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code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock
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if (param(dsp, \ADREG).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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@ -62,8 +63,10 @@ code argQ ffAD ffADmux ffADcepol sigA clock
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ffAD = dff;
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clock = dffclock;
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if (dffcemux) {
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ffADmux = dffcemux;
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ffADcemux = dffcemux;
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ffADrstmux = dffrstmux;
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ffADcepol = dffcepol;
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ffADrstpol = dffrstpol;
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}
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sigA = dffD;
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}
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@ -100,7 +103,7 @@ code sigA sigD
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}
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endcode
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code argQ ffA ffAmux ffAcepol sigA clock ffAD ffADmux ffADcepol
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code argQ ffA ffAcemux ffArstmux ffAcepol ffArstpol sigA clock ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol
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// Only search for ffA if there was a pre-adder
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// (otherwise ffA would have been matched as ffAD)
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if (preAdd) {
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@ -111,8 +114,10 @@ code argQ ffA ffAmux ffAcepol sigA clock ffAD ffADmux ffADcepol
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ffA = dff;
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clock = dffclock;
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if (dffcemux) {
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ffAmux = dffcemux;
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ffAcemux = dffcemux;
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ffArstmux = dffrstmux;
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ffAcepol = dffcepol;
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ffArstpol = dffrstpol;
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}
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sigA = dffD;
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}
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@ -121,14 +126,16 @@ code argQ ffA ffAmux ffAcepol sigA clock ffAD ffADmux ffADcepol
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// And if there wasn't a pre-adder,
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// move AD register to A
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else if (ffAD) {
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log_assert(!ffA && !ffAmux);
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log_assert(!ffA && !ffAcemux && !ffArstmux);
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std::swap(ffA, ffAD);
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std::swap(ffAmux, ffADmux);
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std::swap(ffAcemux, ffADcemux);
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std::swap(ffArstmux, ffADrstmux);
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ffAcepol = ffADcepol;
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ffArstpol = ffADrstpol;
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}
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endcode
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code argQ ffB ffBmux ffBcepol sigB clock
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code argQ ffB ffBcemux ffBrstmux ffBcepol ffBrstpol sigB clock
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if (param(dsp, \BREG).as_int() == 0) {
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argQ = sigB;
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subpattern(in_dffe);
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@ -136,15 +143,17 @@ code argQ ffB ffBmux ffBcepol sigB clock
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ffB = dff;
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clock = dffclock;
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if (dffcemux) {
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ffBmux = dffcemux;
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ffBcemux = dffcemux;
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ffBrstmux = dffrstmux;
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ffBcepol = dffcepol;
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ffBrstpol = dffrstpol;
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}
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sigB = dffD;
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}
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}
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endcode
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code argQ ffD ffDmux ffDcepol sigD clock
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code argQ ffD ffDcemux ffDrstmux ffDcepol ffDrstpol sigD clock
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if (param(dsp, \DREG).as_int() == 0) {
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argQ = sigD;
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subpattern(in_dffe);
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@ -152,8 +161,10 @@ code argQ ffD ffDmux ffDcepol sigD clock
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ffD = dff;
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clock = dffclock;
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if (dffcemux) {
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ffDmux = dffcemux;
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ffDcemux = dffcemux;
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ffDrstmux = dffrstmux;
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ffDcepol = dffcepol;
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ffDrstpol = dffrstpol;
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}
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sigD = dffD;
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}
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@ -255,16 +266,18 @@ code sigC
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sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
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endcode
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code argQ ffC ffCmux ffCcepol sigC clock
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if (param(dsp, \CREG).as_int() == 0) {
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code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
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if (param(dsp, \CREG).as_int() == 0 && sigC != sigP) {
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argQ = sigC;
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subpattern(in_dffe);
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if (dff) {
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ffC = dff;
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clock = dffclock;
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if (dffcemux) {
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ffCmux = dffcemux;
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ffCcemux = dffcemux;
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ffCrstmux = dffrstmux;
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ffCcepol = dffcepol;
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ffCrstpol = dffrstpol;
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}
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sigC = dffD;
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}
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@ -278,67 +291,102 @@ endcode
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// #######################
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subpattern in_dffe
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arg argQ clock ffcepol
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argQ.chunks()) {
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if (!c.wire)
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reject;
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if (c.wire->get_bool_attribute(\keep))
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reject;
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}
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endcode
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match ff
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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filter GetSize(port(ff, \Q)) >= GetSize(argQ)
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slice offset GetSize(port(ff, \Q))
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filter offset+GetSize(argQ) <= GetSize(port(ff, \Q))
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \Q)[offset] === argQ[0]
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set ffoffset offset
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endmatch
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code argQ argD
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{
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if (clock != SigBit()) {
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if (port(ff, \CLK) != clock)
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reject;
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}
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SigSpec Q = port(ff, \Q);
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if (ffoffset + GetSize(argQ) > GetSize(Q))
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reject;
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for (int i = 1; i < GetSize(argQ); i++)
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if (Q[ffoffset+i] != argQ[i])
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reject;
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dff = ff;
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dffclock = port(ff, \CLK);
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dffD = argQ;
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argD = port(ff, \D);
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argQ = Q;
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dffD.replace(argQ, argD);
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// Only search for ffrstmux if dffD only
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// has two (ff, ffrstmux) users
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if (nusers(dffD) > 2)
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argD = SigSpec();
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}
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endcode
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match ffrstmux
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if !argD.empty()
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select ffrstmux->type.in($mux)
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index <SigSpec> port(ffrstmux, \Y) === argD
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choice <IdString> BA {\B, \A}
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// DSP48E1 only supports reset to zero
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select port(ffrstmux, BA).is_fully_zero()
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define <bool> pol (BA == \B)
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set ffrstpol pol
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semioptional
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endmatch
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code argQ
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if (ff) {
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for (auto c : argQ.chunks())
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if (c.wire->get_bool_attribute(\keep))
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reject;
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code argD
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if (ffrstmux) {
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dffrstmux = ffrstmux;
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dffrstpol = ffrstpol;
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argD = port(ffrstmux, ffrstpol ? \A : \B);
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dffD.replace(port(ffrstmux, \Y), argD);
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if (clock != SigBit()) {
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if (port(ff, \CLK) != clock)
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reject;
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}
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dffclock = port(ff, \CLK);
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dff = ff;
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dffD = argQ;
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dffD.replace(port(ff, \Q), port(ff, \D));
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// Only search for ffcemux if argQ has at
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// least 3 users (ff, <upstream>, ffcemux) and
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// its ff.D only has two (ff, ffcemux)
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// Only search for ffrstmux if argQ has at
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// least 3 users (ff, <upstream>, ffrstmux) and
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// dffD only has two (ff, ffrstmux)
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if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
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argQ = SigSpec();
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}
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else {
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dff = nullptr;
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argQ = SigSpec();
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argD = SigSpec();
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}
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else
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dffrstmux = nullptr;
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endcode
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match ffcemux
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if !argQ.empty()
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if !argD.empty()
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select ffcemux->type.in($mux)
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index <SigSpec> port(ffcemux, \Y) === port(ff, \D)
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filter GetSize(port(ffcemux, \Y)) >= GetSize(dffD)
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slice offset GetSize(port(ffcemux, \Y))
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filter offset+GetSize(dffD) <= GetSize(port(ffcemux, \Y))
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filter port(ffcemux, \Y).extract(offset, GetSize(dffD)) == dffD
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index <SigSpec> port(ffcemux, \Y) === argD
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choice <IdString> AB {\A, \B}
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filter offset+GetSize(argQ) <= GetSize(port(ffcemux, \Y))
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filter port(ffcemux, AB).extract(offset, GetSize(argQ)) == argQ
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index <SigSpec> port(ffcemux, AB) === argQ
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define <bool> pol (AB == \A)
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set ffcepol pol
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semioptional
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endmatch
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code
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code argD
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if (ffcemux) {
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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dffD = port(ffcemux, dffcepol ? \B : \A);
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dffD.replace(port(ffcemux, \Y), argD);
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}
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else
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dffcemux = nullptr;
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@ -379,7 +427,6 @@ code argD argQ
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SigSpec BA = port(ffcemux, ffcepol ? \B : \A);
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if (ffoffset + GetSize(argD) > GetSize(BA))
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reject;
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for (int i = 1; i < GetSize(argD); i++)
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if (BA[ffoffset+i] != argD[i])
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reject;
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@ -440,7 +487,7 @@ match ff
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select param(ff, \CLK_POLARITY).as_bool()
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slice offset GetSize(port(ff, \D))
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index <SigSpec> port(ff, \D)[offset] === argD[0]
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index <SigBit> port(ff, \D)[offset] === argD[0]
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filter (!ffcemux && !ffrstmux) || ffoffset == offset
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set ffoffset offset
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