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hierarchy - proc reorder

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This commit is contained in:
Miodrag Milanovic 2019-10-18 09:04:02 +02:00
parent 7785f23719
commit 0d60902fd9
9 changed files with 18 additions and 14 deletions
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1
tests/ecp5/add_sub.ys
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@ -1,5 +1,6 @@
read_verilog add_sub.v read_verilog add_sub.v
hierarchy -top top hierarchy -top top
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module

8
tests/ecp5/adffs.ys
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@ -1,8 +1,8 @@
read_verilog adffs.v read_verilog adffs.v
design -save read design -save read
proc
hierarchy -top adff hierarchy -top adff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module cd adff # Constrain all select calls below inside the top module
@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D select -assert-none t:TRELLIS_FF %% t:* %D
design -load read design -load read
proc
hierarchy -top adffn hierarchy -top adffn
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module cd adffn # Constrain all select calls below inside the top module
@ -20,8 +20,8 @@ select -assert-count 1 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
design -load read design -load read
proc
hierarchy -top dffs hierarchy -top dffs
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module cd dffs # Constrain all select calls below inside the top module
@ -30,8 +30,8 @@ select -assert-count 1 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
design -load read design -load read
proc
hierarchy -top ndffnr hierarchy -top ndffnr
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module cd ndffnr # Constrain all select calls below inside the top module

4
tests/ecp5/dffs.ys
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@ -1,8 +1,8 @@
read_verilog dffs.v read_verilog dffs.v
design -save read design -save read
proc
hierarchy -top dff hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D select -assert-none t:TRELLIS_FF %% t:* %D
design -load read design -load read
proc
hierarchy -top dffe hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module

6
tests/ecp5/latches.ys
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@ -2,8 +2,8 @@
read_verilog latches.v read_verilog latches.v
design -save read design -save read
proc
hierarchy -top latchp hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 synth_ecp5
cd latchp # Constrain all select calls below inside the top module cd latchp # Constrain all select calls below inside the top module
@ -13,8 +13,8 @@ select -assert-none t:LUT4 %% t:* %D
design -load read design -load read
proc
hierarchy -top latchn hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 synth_ecp5
cd latchn # Constrain all select calls below inside the top module cd latchn # Constrain all select calls below inside the top module
@ -24,8 +24,8 @@ select -assert-none t:LUT4 %% t:* %D
design -load read design -load read
proc
hierarchy -top latchsr hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 synth_ecp5
cd latchsr # Constrain all select calls below inside the top module cd latchsr # Constrain all select calls below inside the top module

1
tests/ecp5/logic.ys
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@ -1,5 +1,6 @@
read_verilog logic.v read_verilog logic.v
hierarchy -top top hierarchy -top top
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module

2
tests/ecp5/macc.ys
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@ -1,6 +1,6 @@
read_verilog macc.v read_verilog macc.v
proc
hierarchy -top top hierarchy -top top
proc
# Blocked by issue #1358 (Missing ECP5 simulation models) # Blocked by issue #1358 (Missing ECP5 simulation models)
#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check

1
tests/ecp5/mul.ys
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@ -1,5 +1,6 @@
read_verilog mul.v read_verilog mul.v
hierarchy -top top hierarchy -top top
proc
# Blocked by issue #1358 (Missing ECP5 simulation models) # Blocked by issue #1358 (Missing ECP5 simulation models)
#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check

8
tests/ecp5/mux.ys
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@ -1,8 +1,8 @@
read_verilog mux.v read_verilog mux.v
design -save read design -save read
proc
hierarchy -top mux2 hierarchy -top mux2
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module cd mux2 # Constrain all select calls below inside the top module
@ -10,8 +10,8 @@ select -assert-count 1 t:LUT4
select -assert-none t:LUT4 %% t:* %D select -assert-none t:LUT4 %% t:* %D
design -load read design -load read
proc
hierarchy -top mux4 hierarchy -top mux4
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module cd mux4 # Constrain all select calls below inside the top module
@ -22,8 +22,8 @@ select -assert-count 2 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
design -load read design -load read
proc
hierarchy -top mux8 hierarchy -top mux8
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module cd mux8 # Constrain all select calls below inside the top module
@ -34,8 +34,8 @@ select -assert-count 2 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
design -load read design -load read
proc
hierarchy -top mux16 hierarchy -top mux16
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module

1
tests/ecp5/rom.ys
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@ -1,4 +1,5 @@
read_verilog rom.v read_verilog rom.v
hierarchy -top top
proc proc
flatten flatten
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check