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hierarchy - proc reorder

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This commit is contained in:
Miodrag Milanovic 2019-10-18 09:04:02 +02:00
parent 7785f23719
commit 0d60902fd9
9 changed files with 18 additions and 14 deletions
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8
tests/ecp5/mux.ys
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@ -1,8 +1,8 @@
read_verilog mux.v
design -save read
proc
hierarchy -top mux2
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
@ -10,8 +10,8 @@ select -assert-count 1 t:LUT4
select -assert-none t:LUT4 %% t:* %D
design -load read
proc
hierarchy -top mux4
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
@ -22,8 +22,8 @@ select -assert-count 2 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
design -load read
proc
hierarchy -top mux8
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
@ -34,8 +34,8 @@ select -assert-count 2 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
design -load read
proc
hierarchy -top mux16
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module