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hierarchy - proc reorder

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This commit is contained in:
Miodrag Milanovic 2019-10-18 09:04:02 +02:00
parent 7785f23719
commit 0d60902fd9
9 changed files with 18 additions and 14 deletions
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6
tests/ecp5/latches.ys
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@ -2,8 +2,8 @@
read_verilog latches.v
design -save read
proc
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5
cd latchp # Constrain all select calls below inside the top module
@ -13,8 +13,8 @@ select -assert-none t:LUT4 %% t:* %D
design -load read
proc
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5
cd latchn # Constrain all select calls below inside the top module
@ -24,8 +24,8 @@ select -assert-none t:LUT4 %% t:* %D
design -load read
proc
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5
cd latchsr # Constrain all select calls below inside the top module