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hierarchy - proc reorder

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This commit is contained in:
Miodrag Milanovic 2019-10-18 09:04:02 +02:00
parent 7785f23719
commit 0d60902fd9
9 changed files with 18 additions and 14 deletions
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4
tests/ecp5/dffs.ys
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@ -1,8 +1,8 @@
read_verilog dffs.v
design -save read
proc
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
proc
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module