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hierarchy - proc reorder

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This commit is contained in:
Miodrag Milanovic 2019-10-18 09:04:02 +02:00
parent 7785f23719
commit 0d60902fd9
9 changed files with 18 additions and 14 deletions
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8
tests/ecp5/adffs.ys
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@ -1,8 +1,8 @@
read_verilog adffs.v
design -save read
proc
hierarchy -top adff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
proc
hierarchy -top adffn
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
@ -20,8 +20,8 @@ select -assert-count 1 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
design -load read
proc
hierarchy -top dffs
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
@ -30,8 +30,8 @@ select -assert-count 1 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
design -load read
proc
hierarchy -top ndffnr
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module