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intel_alm: add Cyclone 10 GX tests

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Dan Ravensloft 2020-07-05 18:53:14 +01:00 • committed by Marcelina Kościelnicka
parent b5f3b70cfe
commit 0d4c2f0a65
11 changed files with 241 additions and 7 deletions
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14
tests/arch/intel_alm/quartus_ice.ys
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@ -10,3 +10,17 @@ EOT
synth_intel_alm -family cyclonev -quartus
select -assert-none w:*[* w:*]*
design -reset
read_verilog <<EOT
// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
module top();
(* keep *) wire [31:0] \a[10] ;
(* keep *) wire b;
assign b = \a[10] [31];
endmodule
EOT
synth_intel_alm -family cyclone10gx -quartus
select -assert-none w:*[* w:*]*