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intel_alm: add Cyclone 10 GX tests
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11 changed files with 241 additions and 7 deletions
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@ -1,15 +1,26 @@
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read_verilog ../common/mux.v
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design -save read
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hierarchy -top mux2
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proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-none t:MISTRAL_ALUT3 %% t:* %D
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design -load read
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hierarchy -top mux2
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proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-none t:MISTRAL_ALUT3 %% t:* %D
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design -load read
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hierarchy -top mux4
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proc
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@ -17,9 +28,19 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT6 %% t:* %D
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design -load read
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hierarchy -top mux4
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proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT6 %% t:* %D
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design -load read
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hierarchy -top mux8
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proc
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@ -29,9 +50,20 @@ cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-count 1 t:MISTRAL_ALUT5
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select -assert-count 2 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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design -load read
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hierarchy -top mux8
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proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-count 2 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
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design -load read
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hierarchy -top mux16
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proc
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@ -41,5 +73,17 @@ cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-count 2 t:MISTRAL_ALUT5
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select -assert-count 4 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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design -load read
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hierarchy -top mux16
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proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-count 2 t:MISTRAL_ALUT5
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select -assert-count 4 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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