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Merge branch 'master' into struct

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Peter Crozier 2020-06-03 17:19:28 +01:00 • committed by GitHub
commit 0d3f7ea011
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tests/svtypes/logic_rom.sv Normal file
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module top(input [3:0] addr, output [7:0] data);
logic [7:0] mem[0:15];
assign data = mem[addr];
integer i;
initial for(i = 0; i < 16; i = i + 1) mem[i] = i;
endmodule

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tests/svtypes/logic_rom.ys Normal file
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read_verilog -sv logic_rom.sv
prep -top top
select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i