From 0d3c218d6bec619a90d107f1001f4649a7f05292 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 10 Dec 2025 18:46:44 +0100 Subject: [PATCH] proc_mux: copy mux src to Y port (cherry picked from commit da65a18f39ad48a1c6c27fbe1494a0544739ad10) --- passes/proc/proc_mux.cc | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 89a8f8806..ee9685279 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -508,10 +508,13 @@ RTLIL::SigSpec signal_to_mux_tree(MuxTreeContext ctx) result = mux_gen_ctx.gen_mux(value, result); } } - if (mux_gen_ctx.last_mux_cell && !case_sources.empty()) { - std::vector refs(case_sources.begin(), case_sources.end()); - RTLIL::Cell *cell = mux_gen_ctx.last_mux_cell; - cell->set_src_attribute(cell->module->design->twines.concat(std::span{refs})); + if (auto* mux = mux_gen_ctx.last_mux_cell) { + if (!case_sources.empty()) { + std::vector refs(case_sources.begin(), case_sources.end()); + mux->set_src_attribute(mux->module->design->twines.concat(std::span{refs})); + } + log_assert(mux->getPort(TW::Y).is_wire()); + mux->getPort(TW::Y).as_wire()->transfer_src_attribute(mux); } }