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improved ice40 dff cell mapping

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This commit is contained in:
Clifford Wolf 2015-04-16 11:30:56 +02:00
parent f80d020f17
commit 0d344a23d3
3 changed files with 46 additions and 7 deletions
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8
techlibs/ice40/cells_sim.v
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@ -70,10 +70,10 @@ endmodule
// SiliconBlue Logic Cells
module SB_LUT4 (output O, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule