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preproc: test coverage for #2712
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7
tests/verilog/ifdef_nest.ys
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7
tests/verilog/ifdef_nest.ys
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@ -0,0 +1,7 @@
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read_verilog <<EOF
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`ifndef a
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`ifdef b
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`endif
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`else
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`endif
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EOF
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4
tests/verilog/ifdef_unterminated.ys
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tests/verilog/ifdef_unterminated.ys
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logger -expect error "Unterminated preprocessor conditional!" 1
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read_verilog <<EOF
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`ifndef a
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EOF
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7
tests/verilog/unmatched_endif_2.ys
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7
tests/verilog/unmatched_endif_2.ys
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logger -expect error "Found `endif outside of macro conditional branch!" 1
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read_verilog <<EOF
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`ifndef a
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`else
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`endif
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`endif
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EOF
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