From 0c8e008ce7497c4c891832764e4bc6d9232c6205 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Sun, 2 Nov 2025 11:10:08 +0100
Subject: [PATCH] proc_mux: add src test

---
 tests/proc/proc_mux_src.v  | 92 ++++++++++++++++++++++++++++++++++++++
 tests/proc/proc_mux_src.ys | 33 ++++++++++++++
 2 files changed, 125 insertions(+)
 create mode 100644 tests/proc/proc_mux_src.v
 create mode 100644 tests/proc/proc_mux_src.ys

diff --git a/tests/proc/proc_mux_src.v b/tests/proc/proc_mux_src.v
new file mode 100644
index 000000000..17d6da104
--- /dev/null
+++ b/tests/proc/proc_mux_src.v
@@ -0,0 +1,92 @@
+module nested(
+	input clk,
+	input [7:0] A,
+	input [7:0] B,
+	input [3:0] mode1,
+	input [3:0] mode2,
+	output reg [7:0] result1,
+	output reg [7:0] result2,
+	output reg [1:0] arith
+);
+
+	localparam OP_A = 4'b0000;
+	localparam OP_BA = 4'b0001;
+	localparam OP_BB = 4'b0010;
+	localparam OP_C = 4'b0011;
+
+	always @(posedge clk)
+	begin
+		case (mode1)
+			OP_A: begin
+				result1 = A + B;
+				result2 = A - B;
+				arith = 2'b01;
+			end
+			OP_BA , OP_BB : begin
+				result1 = A * B;
+				result2 = A / B;
+				arith = 2'b00;
+			end
+			OP_C : begin
+				arith = 2'b10;
+				case (mode2)
+					OP_A: begin
+						result1 = ~B;
+						result2 = B;
+					end
+					OP_C: begin
+						result1 = A ^ B;
+						result2 = A == B;
+					end
+					default: begin
+						result1 = 1'b0;
+						// result2 omitted
+					end
+				endcase
+			end
+			default: begin
+				result1 = 8'b0;
+				result2 = 8'b0;
+				arith = 2'b11;
+			end
+		endcase
+	end
+endmodule
+
+module tiny(
+	input clk,
+	input ya,
+	input [7:0] in,
+	output reg [7:0] out,
+);
+	always @(posedge clk)
+	begin
+		case (ya)
+			1'b1: begin
+				out = in;
+			end
+		endcase
+	end
+endmodule
+
+module tiny2(
+	input clk,
+	input [1:0] ya,
+	input [7:0] in,
+	output reg [7:0] out,
+);
+	always @(posedge clk)
+	begin
+		case (ya)
+			2'b01: begin
+				out = in;
+			end
+			2'b10: begin
+				out = 1'b1;
+			end
+			default begin
+				out = 1'b0;
+			end
+		endcase
+	end
+endmodule
diff --git a/tests/proc/proc_mux_src.ys b/tests/proc/proc_mux_src.ys
new file mode 100644
index 000000000..e25858e26
--- /dev/null
+++ b/tests/proc/proc_mux_src.ys
@@ -0,0 +1,33 @@
+read_verilog proc_mux_src.v
+proc -noopt
+check -assert
+# eq refer to the values compared against
+select -assert-count 2 tiny2/t:$eq
+select -assert-count 1 tiny2/t:$eq a:src=proc_mux_src.v:81.4-81.10 %i
+select -assert-count 1 tiny2/t:$eq a:src=proc_mux_src.v:84.4-84.10 %i
+# Flops cover the whole process
+select -assert-count 1 tiny2/t:$dff
+select -assert-count 1 tiny2/t:$dff a:src=proc_mux_src.v:78.2-91.5 %i
+# Muxes are marked to the exact assignment statements they represent including the explicit default case
+select -assert-count 1 tiny2/t:$pmux
+select -assert-count 1 tiny2/t:$pmux a:src=proc_mux_src.v:80.5-80.13|proc_mux_src.v:83.5-83.15|proc_mux_src.v:86.5-86.15
+select -assert-count 0 tiny/t:$reduce_or
+
+# Implicit default cases add src attributes to muxes that cover the whole switch
+select -assert-count 1 tiny/t:$mux
+select -assert-count 1 tiny/t:$mux a:proc_mux_src.v:65.5-65.13|proc_mux_src.v:63.3-67.10
+select -assert-count 0 tiny/t:$reduce_or
+
+dump nested
+#dump nested/t:$pmux
+# $reduce_or src covers the entire list of comparison RHSs
+# Each snippet is treated separately so it gets its own $eq and $reduce_or etc
+select -assert-count 3 nested/t:$reduce_or
+select -assert-count 3 nested/t:$reduce_or a:src=proc_mux_src.v:25.4-25.19 %i
+# When switches are nested, the top mux considers the inner switch the entire source
+# for one of its inputs. Here, that's proc_mux_src.v:32.5-45.12
+select -assert-count 5 nested/t:$pmux
+select -assert-count 1 nested/t:$pmux a:src=proc_mux_src.v:21.5-21.20|proc_mux_src.v:26.5-26.20|proc_mux_src.v:32.5-45.12|proc_mux_src.v:48.5-48.19 %i
+# No nesting for output reg arith
+select -assert-count 1 nested/t:$pmux a:src=proc_mux_src.v:23.5-23.18|proc_mux_src.v:28.5-28.18|proc_mux_src.v:31.5-31.18|proc_mux_src.v:50.5-50.18 %i
+dump nested/t:$pmux