mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
Code Activity

Added SigPool::check(bit)

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 15:38:02 +02:00
parent ddd31a0b66
commit 0c86d6106c
2 changed files with 7 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/opt/opt_clean.cc
View file

@ -251,10 +251,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
for (int i = 0; i < SIZE(sig); i++) {
if (sig[i].wire == NULL)
continue;
if (!used_signals_nodrivers.check_any(sig[i])) {
if (!used_signals_nodrivers.check(sig[i])) {
if (!unused_bits.empty())
unused_bits += " ";
unused_bits += stringf("%zd", i);
unused_bits += stringf("%d", i);
}
}
if (unused_bits.empty() || wire->port_id != 0)