mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-23 22:33:41 +00:00
Code Activity

Move DSP mapping back out to dsp_map.v

Browse source
This commit is contained in:
Eddie Hung 2019-07-15 14:18:44 -07:00
parent 91fcf034bc
commit 0c7ee6d0fa
2 changed files with 40 additions and 41 deletions
Download patch file Download diff file Expand all files Collapse all files

41
techlibs/xilinx/cells_map.v
View file

@ -365,44 +365,3 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O)); MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
endmodule endmodule
`endif `endif
module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
wire [47:0] P_48;
DSP48E1 #(
// Disable all registers
.ACASCREG(0),
.ADREG(0),
.A_INPUT("DIRECT"),
.ALUMODEREG(0),
.AREG(0),
.BCASCREG(0),
.B_INPUT("DIRECT"),
.BREG(0),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(0),
.MREG(0),
.OPMODEREG(0),
.PREG(0)
) _TECHMAP_REPLACE_ (
//Data path
.A({5'b0, A}),
.B(B),
.C(48'b0),
.D(24'b0),
.P(P_48),
.INMODE(4'b0000),
.ALUMODE(4'b0000),
.OPMODE(7'b000101),
.CARRYINSEL(3'b000),
.ACIN(30'b0),
.BCIN(18'b0),
.PCIN(48'b0),
.CARRYIN(1'b0)
);
assign OUT = P_48;
endmodule

40
techlibs/xilinx/dsp_map.v Normal file
View file

@ -0,0 +1,40 @@
module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
wire [47:0] P_48;
DSP48E1 #(
// Disable all registers
.ACASCREG(0),
.ADREG(0),
.A_INPUT("DIRECT"),
.ALUMODEREG(0),
.AREG(0),
.BCASCREG(0),
.B_INPUT("DIRECT"),
.BREG(0),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(0),
.MREG(0),
.OPMODEREG(0),
.PREG(0)
) _TECHMAP_REPLACE_ (
//Data path
.A({5'b0, A}),
.B(B),
.C(48'b0),
.D(24'b0),
.P(P_48),
.INMODE(4'b0000),
.ALUMODE(4'b0000),
.OPMODE(7'b000101),
.CARRYINSEL(3'b000),
.ACIN(30'b0),
.BCIN(18'b0),
.PCIN(48'b0),
.CARRYIN(1'b0)
);
assign Y = P_48;
endmodule