From 0c580cda8147daede5ed75ad36e9e26d7add57e2 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 21 Jul 2026 19:49:53 +0200 Subject: [PATCH] ql_bram_merge: declare the merged BRAM's ports before connecting them --- techlibs/quicklogic/ql_bram_merge.cc | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/techlibs/quicklogic/ql_bram_merge.cc b/techlibs/quicklogic/ql_bram_merge.cc index 35024cc05..f97eef3c3 100644 --- a/techlibs/quicklogic/ql_bram_merge.cc +++ b/techlibs/quicklogic/ql_bram_merge.cc @@ -122,6 +122,29 @@ struct QlBramMergeWorker { return bram1_map; } + void set_bb_instance_port(RTLIL::Cell *merged, TwineRef port, const RTLIL::SigSpec &sig) + { + static const IdString generated = RTLIL::escape_id("ql_bram_merge_blackbox"); + RTLIL::Design *design = module->design; + + RTLIL::Module *mod = design->module(merged->type_impl); + if (mod == nullptr) { + mod = design->addModule(merged->type_impl); + mod->set_bool_attribute(ID::blackbox); + mod->set_bool_attribute(generated); + } + + if (mod->get_bool_attribute(generated) && mod->wire(port) == nullptr) { + std::string name = design->twines.str(port); + RTLIL::Wire *wire = mod->addWire(port, GetSize(sig)); + bool is_output = name.size() >= 8 && name.compare(name.size() - 8, 8, "_RD_DATA") == 0; + (is_output ? wire->port_output : wire->port_input) = true; + mod->fixup_ports(); + } + + merged->setPort(port, sig); + } + void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2) { const TwineRef merged_cell_type = TW($__QLF_TDP36K_MERGED); @@ -144,14 +167,14 @@ struct QlBramMergeWorker { for (auto &it : port_map(false)) { if (bram1->hasPort(it.first)) - merged->setPort(it.second, bram1->getPort(it.first)); + set_bb_instance_port(merged, it.second, bram1->getPort(it.first)); else log_error("Can't find port %s on cell %s!\n", module->design->twines.unescaped_str(it.first), module->design->twines.unescaped_str(bram1->name.ref())); } for (auto &it : port_map(true)) { if (bram2->hasPort(it.first)) - merged->setPort(it.second, bram2->getPort(it.first)); + set_bb_instance_port(merged, it.second, bram2->getPort(it.first)); else log_error("Can't find port %s on cell %s!\n", module->design->twines.unescaped_str(it.first), module->design->twines.unescaped_str(bram2->name.ref())); }