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WIP migration to twine

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This commit is contained in:
Emil J. Tywoniak 2026-06-18 19:27:41 +02:00
parent 96b0ba9581
commit 0c450ce8c8
110 changed files with 1225 additions and 1082 deletions
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11
kernel/constids.inc
View file

@ -306,6 +306,7 @@ X(ACASCREG)
X(ACCUMCI)
X(ACCUMCO)
X(ACIN)
X(ACOUT)
X(AD)
X(ADDEND_NEGATED)
X(ADDR)
@ -334,6 +335,8 @@ X(AOI4)
X(AREG)
X(ARGS)
X(ARGS_WIDTH)
X(ARSHFT17)
X(ARSHFT17_BYPASS)
X(ARST)
X(ARST_POLARITY)
X(ARST_VALUE)
@ -354,6 +357,7 @@ X(B3)
X(B4)
X(BCASCREG)
X(BCIN)
X(BCOUT)
X(BHOLD)
X(BI)
X(BITS_USED)
@ -384,7 +388,9 @@ X(CARRYOUT)
X(CC_L2T4)
X(CC_L2T5)
X(CC_LUT2)
X(CDIN)
X(CDIN_FDBK_SEL)
X(CDOUT)
X(CE)
X(CEA)
X(CEA1)
@ -444,6 +450,8 @@ X(DFF)
X(DHOLD)
X(DIRECTION)
X(DREG)
X(DSP48A)
X(DSP48A1)
X(DSP48E1)
X(DST)
X(DST_EN)
@ -563,6 +571,7 @@ X(LUT5)
X(LUT6)
X(LUT_INIT)
X(M)
X(MACC_PA)
X(MACROCELL_XOR)
X(MASK)
X(MEMID)
@ -610,8 +619,10 @@ X(OUTB_TAP)
X(OVERFLOW)
X(P)
X(PASUB)
X(PASUB_BYPASS)
X(PATTERN)
X(PCIN)
X(PCOUT)
X(PIPELINE_16x16_MULT_REG1)
X(PIPELINE_16x16_MULT_REG2)
X(PORTID)

2
kernel/driver.cc
View file

@ -713,6 +713,8 @@ int main(int argc, char **argv)
total_ns += gc_ns;
timedat.insert(make_tuple(gc_ns,
RTLIL::OwningIdString::garbage_collection_count(), "id_gc"));
total_ns += twine_gc_ns;
timedat.insert(make_tuple(twine_gc_ns, twine_gc_count, "twine_gc"));
total_ns += signorm_ns;
timedat.insert(make_tuple(signorm_ns, signorm_count, "signorm"));
total_ns += signorm_restore_ns;

2
kernel/register.cc
View file

@ -58,6 +58,8 @@ void try_collect_garbage()
return;
garbage_collection_requested = false;
RTLIL::OwningIdString::collect_garbage();
for (auto &[idx, design] : *RTLIL::Design::get_all_designs())
design->gc_twines();
}
Pass::Pass(std::string name, std::string short_help, source_location location) :

136
kernel/rtlil.cc
View file

@ -1225,8 +1225,12 @@ namespace {
}
}
int64_t twine_gc_ns;
int twine_gc_count;
size_t RTLIL::Design::gc_twines()
{
int64_t start = PerformanceTimer::query();
// Mark phase: gather every TwineRef stored on a live object as a root.
// TwinePool::gc traces each root's concat/suffix children transitively.
pool<TwineRef> live;
@ -1264,7 +1268,13 @@ size_t RTLIL::Design::gc_twines()
}
// Sweep: backing refs are stable, so survivors need no remapping.
return twines.gc(live);
size_t erased = twines.gc(live);
int64_t time_ns = PerformanceTimer::query() - start;
Pass::subtract_from_current_runtime_ns(time_ns);
twine_gc_ns += time_ns;
++twine_gc_count;
return erased;
}
pool<std::string> RTLIL::Design::src_leaves(const RTLIL::AttrObject *obj) const
@ -2028,12 +2038,6 @@ namespace {
int param_bool(IdString name)
{
std::cout << name.str() << "\n";
std::cout << "get\n";
for (auto& [key, val] : cell->parameters) {
std::cout << key.str() << " = ";
std::cout << val.as_string() << "\n";
}
int v = param(name);
if (GetSize(cell->parameters.at(name)) > 32)
error(__LINE__);
@ -3772,6 +3776,12 @@ RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, Twine &&type)
return addCell(std::move(name), design->twines.add(std::move(type)));
}
RTLIL::Cell *RTLIL::Module::addCell(Twine name, Twine type)
{
log_assert(design);
return addCell(design->twines.add(std::move(name)), design->twines.add(std::move(type)));
}
RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, const RTLIL::Cell *other)
{
RTLIL::Cell *cell = addCell(name, other->type_impl);
@ -3919,7 +3929,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed, TwineRef src) { \
@ -3944,7 +3954,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->parameters[ID::WIDTH] = sig_a.size(); \
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed, TwineRef src) { \
@ -3966,7 +3976,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::B, sig_b); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, TwineRef src) { \
@ -4009,7 +4019,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::B, sig_b); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, TwineRef src) { \
@ -4034,7 +4044,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::B, sig_b); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, TwineRef src) { \
@ -4054,7 +4064,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::B, sig_b); \
cell->setPort(TW::S, sig_s); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src) { \
@ -4075,7 +4085,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::S, sig_s); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src) { \
@ -4094,7 +4104,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::B, sig_b); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src) { \
@ -4110,7 +4120,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _type); \
cell->setPort(TW::_P1, sig1); \
cell->setPort(TW::_P2, sig2); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigBit &sig1, TwineRef src) { \
@ -4124,7 +4134,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::_P1, sig1); \
cell->setPort(TW::_P2, sig2); \
cell->setPort(TW::_P3, sig3); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, TwineRef src) { \
@ -4139,7 +4149,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::_P2, sig2); \
cell->setPort(TW::_P3, sig3); \
cell->setPort(TW::_P4, sig4); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, TwineRef src) { \
@ -4155,7 +4165,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::_P3, sig3); \
cell->setPort(TW::_P4, sig4); \
cell->setPort(TW::_P5, sig5); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, TwineRef src) { \
@ -4195,7 +4205,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a);
cell->setPort(TW::B, sig_b);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4208,7 +4218,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::C, sig_c);
cell->setPort(TW::X, sig_x);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4220,7 +4230,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->parameters[ID::OFFSET] = offset;
cell->setPort(TW::A, sig_a);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4232,7 +4242,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a);
cell->setPort(TW::B, sig_b);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4243,7 +4253,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->parameters[ID::WIDTH] = sig_a.size();
cell->setPort(TW::A, sig_a);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4254,7 +4264,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a);
cell->setPort(TW::EN, sig_en);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4263,7 +4273,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), TW($assert));
cell->setPort(TW::A, sig_a);
cell->setPort(TW::EN, sig_en);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4272,7 +4282,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), TW($assume));
cell->setPort(TW::A, sig_a);
cell->setPort(TW::EN, sig_en);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4281,7 +4291,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), TW($live));
cell->setPort(TW::A, sig_a);
cell->setPort(TW::EN, sig_en);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4290,7 +4300,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), TW($fair));
cell->setPort(TW::A, sig_a);
cell->setPort(TW::EN, sig_en);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4299,7 +4309,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), TW($cover));
cell->setPort(TW::A, sig_a);
cell->setPort(TW::EN, sig_en);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4309,7 +4319,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a);
cell->setPort(TW::B, sig_b);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4322,7 +4332,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::SET, sig_set);
cell->setPort(TW::CLR, sig_clr);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4332,7 +4342,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->parameters[ID::WIDTH] = sig_q.size();
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4344,7 +4354,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::CLK, sig_clk);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4358,7 +4368,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::EN, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4375,7 +4385,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::CLR, sig_clr);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4394,7 +4404,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::CLR, sig_clr);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4410,7 +4420,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::ARST, sig_arst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4428,7 +4438,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::ARST, sig_arst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4444,7 +4454,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::D, sig_d);
cell->setPort(TW::AD, sig_ad);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4462,7 +4472,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::D, sig_d);
cell->setPort(TW::AD, sig_ad);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4478,7 +4488,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::SRST, sig_srst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4496,7 +4506,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::SRST, sig_srst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4514,7 +4524,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::SRST, sig_srst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4526,7 +4536,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::EN, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4542,7 +4552,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::ARST, sig_arst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4559,7 +4569,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::CLR, sig_clr);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4574,7 +4584,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::S, sig_set);
cell->setPort(TW::R, sig_clr);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4583,7 +4593,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), TW($_FF_));
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4594,7 +4604,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::C, sig_clk);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4606,7 +4616,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::E, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4620,7 +4630,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::R, sig_clr);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4635,7 +4645,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::E, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4648,7 +4658,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::R, sig_arst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4662,7 +4672,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::E, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4676,7 +4686,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::D, sig_d);
cell->setPort(TW::AD, sig_ad);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4691,7 +4701,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::D, sig_d);
cell->setPort(TW::AD, sig_ad);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4704,7 +4714,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::R, sig_srst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4718,7 +4728,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::E, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4732,7 +4742,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::E, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4743,7 +4753,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::E, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4756,7 +4766,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::R, sig_arst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4770,7 +4780,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::R, sig_clr);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}

14
kernel/rtlil.h
View file

@ -146,6 +146,8 @@ extern int64_t signorm_ns;
extern int signorm_count;
extern int64_t signorm_restore_ns;
extern int signorm_restore_count;
extern int64_t twine_gc_ns;
extern int twine_gc_count;
struct RTLIL::IdString
{
@ -592,7 +594,10 @@ public:
}
};
inline bool operator==(TwineRef a, RTLIL::IdString b) { return a.untag().value == (size_t)(unsigned)b.index_; }
inline bool operator==(TwineRef a, RTLIL::IdString b) {
size_t bi = (size_t)(unsigned)b.index_;
return bi != 0 && a.untag().value + 1 == bi;
}
inline bool operator==(RTLIL::IdString a, TwineRef b) { return b == a; }
struct RTLIL::OwningIdString : public RTLIL::IdString {
@ -1381,7 +1386,7 @@ struct NameMasqBase {
bool operator==(const Derived &rhs) const { return self().ref() == rhs.ref(); }
bool operator!=(const Derived &rhs) const { return self().ref() != rhs.ref(); }
bool operator<(const Derived &rhs) const { return self().escaped() < rhs.escaped(); }
[[nodiscard]] Hasher hash_into(Hasher h) const { return RTLIL::IdString(self()).hash_into(h); }
[[nodiscard]] Hasher hash_into(Hasher h) const { return self().ref().hash_into(h); }
private:
const Derived &self() const { return *static_cast<const Derived *>(this); }
};
@ -2331,7 +2336,7 @@ public:
friend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design, bool resolve_src);
RTLIL::Cell *driverCell_ = nullptr;
TwineRef driverPort_;
TwineRef driverPort_ = Twine::Null;
// do not simply copy wires
Wire(ConstructToken, RTLIL::Wire &other);
@ -3160,6 +3165,9 @@ public:
RTLIL::Cell *addCell(TwineRef name, Twine &&type);
RTLIL::Cell *addCell(Twine &&name, const RTLIL::Cell *other);
// CellAdderMixin hook: cells added here are attached, so set src directly.
void cell_set_src(RTLIL::Cell *cell, TwineRef src) { cell->set_src_attribute(src); }
// NEW_ID analog for twine names; see NEW_TWINE in yosys_common.h.
TwineRef new_name(const std::string *prefix) {
TwineRef pref = design->twines.add(Twine{*prefix});

4
kernel/rtlil_bufnorm.cc
View file

@ -1015,6 +1015,10 @@ void RTLIL::Cell::unsetPort(TwineRef portname)
if (bit.is_wire()) {
auto found = fanout.find(bit);
log_assert(found != fanout.end());
// log("debug erasing %s\n", module->design->twines.str(portname));
// log("debug erasing %s %s %d\n", name, module->design->twines.str(portname), i);
// for (auto portbit : found->second)
// log("pb %s %s %d\n", portbit.cell->name, module->design->twines.str(portbit.port), portbit.offset);
int erased = found->second.erase(PortBit(this, portname, i));
log_assert(erased);
if (found->second.empty())

10
kernel/twine.h
View file

@ -108,7 +108,7 @@ struct TW {
}
};
#define TW(id) (size_t)lookup_well_known_id(#id)
#define TW(id) ((size_t)std::integral_constant<int, lookup_well_known_id(#id)>::value)
// #define TW(name) TW::lookup(#name)
struct Twine {
@ -294,6 +294,14 @@ struct TwinePool {
return Twine::Null;
}
// Escaped-name aware: strips a leading '\' and tags the result public,
// mirroring add(std::string), then resolves the content against the
// structural index. Returns Twine::Null if absent.
TwineRef find(const std::string &name) const {
bool is_public = !name.empty() && name[0] == '\\';
return find(Twine{is_public ? name.substr(1) : name}).tag(is_public);
}
TwineRef add_inner(Twine t) {
// Nodes store content only: strip publicity tags off child handles.
if (auto *children = std::get_if<std::vector<TwineRef>>(&t.data)) {

8
kernel/unstable/patch.cc
View file

@ -83,6 +83,8 @@ Wire* Patch::commit_wire(std::unique_ptr<Wire> wire) {
Wire* raw = wire.release();
TwineRef id = twine_staging.resolve(staged_wire_names_.at(raw));
staged_wire_names_.erase(raw);
if (!raw->meta_)
raw->meta_ = mod->design->alloc_obj_meta();
raw->meta_->name = id;
mod->wires_[raw->meta_->name] = raw;
raw->module = mod;
@ -93,9 +95,15 @@ Cell* Patch::commit_cell(std::unique_ptr<Cell> cell) {
Cell* raw = cell.release();
TwineRef id = twine_staging.resolve(staged_cell_names_.at(raw));
staged_cell_names_.erase(raw);
if (!raw->meta_)
raw->meta_ = mod->design->alloc_obj_meta();
raw->meta_->name = id;
raw->module = mod;
mod->cells_[raw->meta_->name] = raw;
if (auto it = staged_cell_src_.find(raw); it != staged_cell_src_.end()) {
raw->set_src_attribute(twine_staging.resolve(it->second));
staged_cell_src_.erase(it);
}
raw->initIndex();
return raw;
}

8
kernel/unstable/patch.h
View file

@ -28,6 +28,7 @@ public:
vector<std::unique_ptr<Cell>> cells_ = {};
TwineChildPool twine_staging;
dict<RTLIL::Cell*, TwineRef> staged_cell_names_;
dict<RTLIL::Cell*, TwineRef> staged_cell_src_;
dict<RTLIL::Wire*, TwineRef> staged_wire_names_;
dict<const std::string*, TwineRef> staged_prefix_cache_;
@ -80,6 +81,13 @@ public:
RTLIL::Cell *addCell(Twine &&name, TwineRef type);
RTLIL::Cell *addCell(TwineRef name, Twine &&type);
// CellAdderMixin hook: staged cells are detached, so record the src and
// apply it once the cell is committed (commit_cell), resolving it through
// twine_staging so the ref may be twine_staging-local (interned without
// touching the per-Design pool). patch()/patch_ports() may still override
// it via apply_src merging from the rewritten cell.
void cell_set_src(RTLIL::Cell *cell, TwineRef src) { if (src != Twine::Null) staged_cell_src_[cell] = src; }
// NEW_ID analog for twine names; see NEW_TWINE in yosys_common.h.
// Returned refs are twine_staging-local and die at the next commit.
TwineRef new_name(const std::string *prefix);