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Count $_NOT_ cells turned into $luts

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This commit is contained in:
Eddie Hung 2019-07-11 09:55:14 -07:00
parent 33862d0445
commit 0c3ed73dad
1 changed files with 2 additions and 7 deletions
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9
passes/techmap/abc9.cc
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@ -584,7 +584,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
log_assert(wire); log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1); module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1);
} }
else if (!lut_costs.empty() || !lut_file.empty()) { else {
RTLIL::Cell* driving_lut = nullptr; RTLIL::Cell* driving_lut = nullptr;
// ABC can return NOT gates that drive POs // ABC can return NOT gates that drive POs
if (!a_bit.wire->port_input) { if (!a_bit.wire->port_input) {
@ -622,12 +622,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset), RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
driver_lut); driver_lut);
} }
} cell_stats["$lut"]++;
else {
cell = module->addCell(remap_name(c->name), "$_NOT_");
cell->setPort("\\A", RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset));
cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
cell_stats[RTLIL::unescape_id(c->type)]++;
} }
if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
continue; continue;