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https://github.com/YosysHQ/yosys
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analogdevices: update T40LP timings
This commit is contained in:
Lofty
parent
c6d48eb1e1
commit
0bffb625c3
1 changed files with 157 additions and 142 deletions
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@ -43,7 +43,7 @@ module INBUF(
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`endif
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`ifdef IS_T40LP
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specify
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(I => O) = 121;
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(I => O) = 187;
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endspecify
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`endif
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endmodule
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@ -64,7 +64,7 @@ module OUTBUF(
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`endif
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`ifdef IS_T40LP
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specify
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(I => O) = 121;
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(I => O) = 187;
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endspecify
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`endif
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endmodule
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@ -394,55 +394,61 @@ module CRY4(
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(S[1] => O[3]) = 160;
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(S[2] => O[3]) = 97;
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(S[3] => O[3]) = 39;
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endspecify
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`endif
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`ifdef IS_T40LP
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specify
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(S[0] => O[0]) = 128;
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(CI => O[0]) = 122;
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(DI[0] => O[1]) = 268;
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(S[0] => O[1]) = 256;
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(S[1] => O[1]) = 141;
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(CI => O[1]) = 173;
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(DI[0] => O[2]) = 344;
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(DI[1] => O[2]) = 320;
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(S[0] => O[2]) = 271;
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(S[1] => O[2]) = 225;
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(S[2] => O[2]) = 129;
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(CI => O[2]) = 223;
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(DI[0] => O[3]) = 371;
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(DI[1] => O[3]) = 383;
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(DI[2] => O[3]) = 327;
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(S[0] => O[3]) = 342;
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(S[1] => O[3]) = 327;
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(S[2] => O[3]) = 273;
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(S[3] => O[3]) = 145;
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(CI => O[3]) = 301;
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(DI[0] => CO[0]) = 243;
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(S[0] => CO[0]) = 136;
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(CI => CO[0]) = 119;
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(DI[0] => CO[1]) = 242;
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(DI[1] => CO[1]) = 251;
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(S[0] => CO[1]) = 220;
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(S[1] => CO[1]) = 159;
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(CI => CO[1]) = 155;
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(DI[0] => CO[2]) = 275;
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(DI[1] => CO[2]) = 241;
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(DI[2] => CO[2]) = 231;
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(S[0] => CO[2]) = 238;
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(S[1] => CO[2]) = 197;
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(S[2] => CO[2]) = 167;
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(CI => CO[2]) = 197;
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(DI[0] => CO[3]) = 294;
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(DI[1] => CO[3]) = 303;
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(DI[2] => CO[3]) = 317;
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(CI => CO[0]) = 132;
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(DI[0] => CO[0]) = 245;
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(S[0] => CO[0]) = 218;
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(CI => CO[1]) = 183;
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(DI[0] => CO[1]) = 261;
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(DI[1] => CO[1]) = 325;
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(S[0] => CO[1]) = 270;
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(S[1] => CO[1]) = 199;
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(CI => CO[2]) = 218;
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(DI[0] => CO[2]) = 284;
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(DI[1] => CO[2]) = 345;
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(DI[2] => CO[2]) = 242;
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(S[0] => CO[2]) = 334;
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(S[1] => CO[2]) = 271;
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(S[2] => CO[2]) = 228;
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(CI => CO[3]) = 258;
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(DI[0] => CO[3]) = 334;
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(DI[1] => CO[3]) = 395;
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(DI[2] => CO[3]) = 342;
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(DI[3] => CO[3]) = 205;
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(S[0] => CO[3]) = 250;
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(S[1] => CO[3]) = 292;
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(S[2] => CO[3]) = 231;
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(S[3] => CO[3]) = 178;
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(CI => CO[3]) = 229;
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(S[0] => CO[3]) = 382;
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(S[1] => CO[3]) = 321;
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(S[2] => CO[3]) = 324;
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(S[3] => CO[3]) = 252;
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(CI => O[0]) = 123;
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(S[0] => O[0]) = 150;
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(CI => O[1]) = 265;
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(DI[0] => O[1]) = 331;
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(S[0] => O[1]) = 292;
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(S[1] => O[1]) = 151;
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(CI => O[2]) = 288;
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(DI[0] => O[2]) = 371;
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(DI[1] => O[2]) = 407;
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(S[0] => O[2]) = 391;
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(S[1] => O[2]) = 314;
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(S[2] => O[2]) = 144;
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(CI => O[3]) = 313;
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(DI[0] => O[3]) = 388;
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(DI[1] => O[3]) = 432;
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(DI[2] => O[3]) = 335;
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(S[0] => O[3]) = 418;
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(S[1] => O[3]) = 357;
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(S[2] => O[3]) = 331;
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(S[3] => O[3]) = 145;
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endspecify
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`endif
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endmodule
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@ -492,11 +498,11 @@ module FFRE (
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D , posedge C, 119);
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$setup(CE, posedge C, 385);
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$setup(R , posedge C, 565);
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if (R) (posedge C => (Q : 1'b0)) = 672;
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if (!R && CE) (posedge C => (Q : D)) = 672;
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$setup(D , posedge C, 144);
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$setup(CE, posedge C, 412);
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$setup(R , posedge C, 667);
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if (R) (posedge C => (Q : 1'b0)) = 712;
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if (!R && CE) (posedge C => (Q : D)) = 712;
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endspecify
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`endif
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endmodule
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@ -524,11 +530,11 @@ module FFRE_N (
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D , negedge C, 119);
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$setup(CE, negedge C, 385);
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$setup(R , negedge C, 565);
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if (R) (negedge C => (Q : 1'b0)) = 672;
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if (!R && CE) (negedge C => (Q : D)) = 672;
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$setup(D , negedge C, 144);
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$setup(CE, negedge C, 412);
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$setup(R , negedge C, 667);
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if (R) (negedge C => (Q : 1'b0)) = 712;
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if (!R && CE) (negedge C => (Q : D)) = 712;
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endspecify
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`endif
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endmodule
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@ -622,12 +628,12 @@ module FFCE (
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D , posedge C, 119);
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$setup(CE, posedge C, 385);
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$setup(CLR, posedge C, 0 /* missing? */);
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if (!CLR && CE) (posedge C => (Q : D)) = 689;
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$setup(D , posedge C, 140);
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$setup(CE, posedge C, 412);
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$setup(CLR, posedge C, 6);
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if (!CLR && CE) (posedge C => (Q : D)) = 55;
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`ifdef YOSYS
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if (CLR) (CLR => Q) = 0 /* missing? */;
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if (CLR) (CLR => Q) = 55;
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`endif
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endspecify
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`endif
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@ -658,12 +664,12 @@ module FFCE_N (
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D, negedge C, 119);
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$setup(CE, negedge C, 385);
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$setup(CLR, negedge C, 0 /* missing? */);
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if (!CLR && CE) (negedge C => (Q : D)) = 689;
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$setup(D, negedge C, 140);
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$setup(CE, negedge C, 412);
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$setup(CLR, negedge C, 6);
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if (!CLR && CE) (negedge C => (Q : D)) = 55;
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`ifdef YOSYS
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if (CLR) (CLR => Q) = 0 /* missing? */;
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if (CLR) (CLR => Q) = 55;
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`endif
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endspecify
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`endif
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@ -693,12 +699,12 @@ module FFPE (
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D, posedge C, 119);
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$setup(CE, posedge C, 385);
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$setup(PRE, posedge C, 0 /* missing? */);
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if (!PRE && CE) (posedge C => (Q : D)) = 672;
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$setup(D, posedge C, 140);
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$setup(CE, posedge C, 412);
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$setup(PRE, posedge C, 6);
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if (!PRE && CE) (posedge C => (Q : D)) = 55;
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`ifdef YOSYS
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if (PRE) (PRE => Q) = 0 /* missing? */;
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if (PRE) (PRE => Q) = 55;
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`endif
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endspecify
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`endif
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@ -728,9 +734,9 @@ module FFPE_N (
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`endif
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`ifdef IS_T40LP
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specify
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$setup(D, negedge C, 84);
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$setup(CE, negedge C, 84);
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$setup(PRE, negedge C, 84);
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$setup(D, negedge C, 89);
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$setup(CE, negedge C, 89);
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$setup(PRE, negedge C, 89);
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if (!PRE && CE) (negedge C => (Q : D)) = 712;
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`ifdef YOSYS
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if (PRE) (PRE => Q) = 57;
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@ -776,18 +782,18 @@ module RAMS32X1 (
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`endif
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`ifdef IS_T40LP
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specify
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$setup(A0, posedge WCLK, 84);
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$setup(A1, posedge WCLK, 84);
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$setup(A2, posedge WCLK, 84);
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$setup(A3, posedge WCLK, 84);
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$setup(A4, posedge WCLK, 84);
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$setup(D, posedge WCLK, 84);
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$setup(WE, posedge WCLK, 84);
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(A0 => O) = 168;
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(A1 => O) = 168;
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(A2 => O) = 168;
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(A3 => O) = 168;
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(A4 => O) = 168;
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$setup(A0, posedge WCLK, 198);
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$setup(A1, posedge WCLK, 198);
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$setup(A2, posedge WCLK, 198);
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$setup(A3, posedge WCLK, 198);
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$setup(A4, posedge WCLK, 198);
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$setup(D, posedge WCLK, 198);
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$setup(WE, posedge WCLK, 198);
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(A0 => O) = 211;
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(A1 => O) = 202;
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(A2 => O) = 193;
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(A3 => O) = 185;
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(A4 => O) = 176;
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(posedge WCLK => (O : D)) = 1586;
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endspecify
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`endif
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@ -828,19 +834,19 @@ module RAMS64X1 (
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`endif
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`ifdef IS_T40LP
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specify
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$setup(A0, posedge WCLK, 84);
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$setup(A1, posedge WCLK, 84);
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$setup(A2, posedge WCLK, 84);
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$setup(A3, posedge WCLK, 84);
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$setup(A4, posedge WCLK, 84);
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$setup(A5, posedge WCLK, 84);
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$setup(D, posedge WCLK, 84);
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$setup(WE, posedge WCLK, 84);
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(A0 => O) = 466;
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(A1 => O) = 466;
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(A2 => O) = 466;
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(A3 => O) = 466;
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(A4 => O) = 466;
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$setup(A0, posedge WCLK, 224);
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$setup(A1, posedge WCLK, 224);
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$setup(A2, posedge WCLK, 224);
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$setup(A3, posedge WCLK, 224);
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$setup(A4, posedge WCLK, 224);
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$setup(A5, posedge WCLK, 224);
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$setup(D, posedge WCLK, 224);
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$setup(WE, posedge WCLK, 224);
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(A0 => O) = 509;
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(A1 => O) = 500;
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(A2 => O) = 491;
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(A3 => O) = 483;
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(A4 => O) = 474;
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(A5 => O) = 187;
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(posedge WCLK => (O : D)) = 1730;
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endspecify
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@ -891,26 +897,23 @@ module RAMD32X1 (
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`endif
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`ifdef IS_T40LP
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specify
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// HACK: partial setup timing
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$setup(A0, posedge WCLK, 84);
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$setup(A1, posedge WCLK, 84);
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$setup(A2, posedge WCLK, 84);
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$setup(A3, posedge WCLK, 84);
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$setup(A4, posedge WCLK, 84);
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$setup(D, posedge WCLK, 84);
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$setup(WE, posedge WCLK, 84);
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// HACK: No timing arcs for SPO; using ones for DPO
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// (are we meant to use the single-port timings here?)
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(A0 => SPO) = 142;
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(A1 => SPO) = 142;
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(A2 => SPO) = 142;
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(A3 => SPO) = 142;
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(A4 => SPO) = 142;
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(DPRA0 => DPO) = 142;
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(DPRA1 => DPO) = 142;
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(DPRA2 => DPO) = 142;
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(DPRA3 => DPO) = 142;
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(DPRA4 => DPO) = 142;
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$setup(A0, posedge WCLK, 198);
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$setup(A1, posedge WCLK, 198);
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$setup(A2, posedge WCLK, 198);
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$setup(A3, posedge WCLK, 198);
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$setup(A4, posedge WCLK, 198);
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$setup(D, posedge WCLK, 198);
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$setup(WE, posedge WCLK, 198);
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(A0 => SPO) = 211;
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(A1 => SPO) = 202;
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(A2 => SPO) = 193;
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(A3 => SPO) = 185;
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(A4 => SPO) = 176;
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(DPRA0 => DPO) = 185;
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(DPRA1 => DPO) = 176;
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(DPRA2 => DPO) = 167;
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(DPRA3 => DPO) = 159;
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(DPRA4 => DPO) = 150;
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(posedge WCLK => (SPO : D)) = 1586;
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(posedge WCLK => (DPO : D)) = 1586;
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endspecify
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@ -962,29 +965,28 @@ module RAMD64X1 (
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`endif
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`ifdef IS_T40LP
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specify
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// HACK: partial setup timing
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$setup(A0, posedge WCLK, 84);
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$setup(A1, posedge WCLK, 84);
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$setup(A2, posedge WCLK, 84);
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$setup(A3, posedge WCLK, 84);
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$setup(A4, posedge WCLK, 84);
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$setup(A5, posedge WCLK, 84);
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$setup(D, posedge WCLK, 84);
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$setup(WE, posedge WCLK, 84);
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(A0 => SPO) = 466;
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(A1 => SPO) = 466;
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(A2 => SPO) = 466;
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(A3 => SPO) = 466;
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(A4 => SPO) = 466;
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$setup(A0, posedge WCLK, 224);
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$setup(A1, posedge WCLK, 224);
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$setup(A2, posedge WCLK, 224);
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$setup(A3, posedge WCLK, 224);
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$setup(A4, posedge WCLK, 224);
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$setup(A5, posedge WCLK, 224);
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$setup(D, posedge WCLK, 224);
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$setup(WE, posedge WCLK, 224);
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(A0 => SPO) = 509;
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(A1 => SPO) = 500;
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(A2 => SPO) = 491;
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(A3 => SPO) = 483;
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(A4 => SPO) = 474;
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(A5 => SPO) = 187;
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(DPRA0 => DPO) = 380;
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(DPRA1 => DPO) = 380;
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(DPRA2 => DPO) = 380;
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(DPRA3 => DPO) = 380;
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(DPRA4 => DPO) = 380;
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(DPRA5 => DPO) = 195;
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(posedge WCLK => (SPO : D)) = 1730;
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(posedge WCLK => (DPO : D)) = 1799;
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(DPRA0 => DPO) = 531;
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(DPRA1 => DPO) = 522;
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(DPRA2 => DPO) = 513;
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(DPRA3 => DPO) = 505;
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(DPRA4 => DPO) = 496;
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(DPRA5 => DPO) = 199;
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(posedge WCLK => (SPO : D)) = 1798;
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(posedge WCLK => (DPO : D)) = 1807;
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endspecify
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`endif
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endmodule
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@ -1143,9 +1145,22 @@ module RBRAM #(
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input PD
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);
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// Timings simplified for now
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specify
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$setup(DA, posedge CLKA, 715);
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$setup(CEA, posedge CLKA, 414);
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$setup(AA, posedge CLKA, 624);
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$setup(DB, posedge CLKB, 744);
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$setup(CEB, posedge CLKB, 350);
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$setup(AB, posedge CLKB, 643);
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(posedge CLKA => (QA : DA)) = 2380;
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(posedge CLKB => (QB : DB)) = 2289;
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endspecify
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endmodule
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(* lib_whitebox *)
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module RBRAM2 #(
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parameter TARGET_NODE = "T16FFC_Gen2.4",
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parameter BRAM_MODE = "SDP_2048x40",
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