mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-25 21:57:01 +00:00
Code Activity

Drive-by modernization in sat.cc

Browse source 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
This commit is contained in:
Claire Wolf 2020-06-09 21:49:43 +02:00
parent 3c7122c378
commit 0bd70e8222
1 changed files with 4 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/sat/sat.cc
View file

@ -256,13 +256,13 @@ struct SatHelper
{ {
RTLIL::SigSpec big_lhs, big_rhs; RTLIL::SigSpec big_lhs, big_rhs;
for (auto &it : module->wires_) for (auto wire : module->wires())
{ {
if (it.second->attributes.count(ID::init) == 0) if (wire->attributes.count(ID::init) == 0)
continue; continue;
RTLIL::SigSpec lhs = sigmap(it.second); RTLIL::SigSpec lhs = sigmap(wire);
RTLIL::SigSpec rhs = it.second->attributes.at(ID::init); RTLIL::SigSpec rhs = wire->attributes.at(ID::init);
log_assert(lhs.size() == rhs.size()); log_assert(lhs.size() == rhs.size());
RTLIL::SigSpec removed_bits; RTLIL::SigSpec removed_bits;