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Added "yosys -D" feature

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This commit is contained in:
Clifford Wolf 2016-04-21 23:28:37 +02:00
parent 1565d1af69
commit 0bc95f1e04
113 changed files with 172 additions and 145 deletions
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2
passes/cmds/check.cc
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@ -68,7 +68,7 @@ struct CheckPass : public Pass {
}
extra_args(args, argidx, design);
log_header("Executing CHECK pass (checking for obvious problems).\n");
log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
for (auto module : design->selected_whole_modules_warn())
{

2
passes/cmds/connwrappers.cc
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@ -198,7 +198,7 @@ struct ConnwrappersPass : public Pass {
}
extra_args(args, argidx, design);
log_header("Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
log_header(design, "Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))

2
passes/cmds/cover.cc
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@ -124,7 +124,7 @@ struct CoverPass : public Pass {
extra_args(args, argidx, design);
if (do_log) {
log_header("Printing code coverage counters.\n");
log_header(design, "Printing code coverage counters.\n");
log("\n");
}

2
passes/cmds/qwp.cc
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@ -787,7 +787,7 @@ struct QwpPass : public Pass {
QwpConfig config;
xorshift32_state = 123456789;
log_header("Executing QWP pass (quadratic wirelength placer).\n");
log_header(design, "Executing QWP pass (quadratic wirelength placer).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/cmds/scc.cc
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@ -264,7 +264,7 @@ struct SccPass : public Pass {
int maxDepth = -1;
int expect = -1;
log_header("Executing SCC pass (detecting logic loops).\n");
log_header(design, "Executing SCC pass (detecting logic loops).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

4
passes/cmds/show.cc
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@ -651,7 +651,7 @@ struct ShowPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Generating Graphviz representation of design.\n");
log_header(design, "Generating Graphviz representation of design.\n");
log_push();
std::vector<std::pair<std::string, RTLIL::Selection>> color_selections;
@ -784,7 +784,7 @@ struct ShowPass : public Pass {
}
if (libs.size() > 0)
log_header("Continuing show pass.\n");
log_header(design, "Continuing show pass.\n");
std::string dot_file = stringf("%s.dot", prefix.c_str());
std::string out_file = stringf("%s.%s", prefix.c_str(), format.empty() ? "svg" : format.c_str());

2
passes/cmds/splice.cc
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@ -341,7 +341,7 @@ struct SplicePass : public Pass {
if (!ports.empty() && !no_ports.empty())
log_cmd_error("The options -port and -no_port are exclusive!\n");
log_header("Executing SPLICE pass (creating cells for signal splicing).\n");
log_header(design, "Executing SPLICE pass (creating cells for signal splicing).\n");
for (auto &mod_it : design->modules_)
{

2
passes/cmds/splitnets.cc
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@ -109,7 +109,7 @@ struct SplitnetsPass : public Pass {
bool flag_driver = false;
std::string format = "[]:";
log_header("Executing SPLITNETS pass (splitting up multi-bit signals).\n");
log_header(design, "Executing SPLITNETS pass (splitting up multi-bit signals).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
passes/cmds/stat.cc
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@ -232,7 +232,7 @@ struct StatPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Printing statistics.\n");
log_header(design, "Printing statistics.\n");
bool width_mode = false;
RTLIL::Module *top_mod = NULL;

2
passes/cmds/torder.cc
View file

@ -48,7 +48,7 @@ struct TorderPass : public Pass {
bool noautostop = false;
dict<IdString, pool<IdString>> stop_db;
log_header("Executing TORDER pass (print cells in topological order).\n");
log_header(design, "Executing TORDER pass (print cells in topological order).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {