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changes made to filenames + references

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C77874 2024-07-04 08:53:41 -07:00
parent e5bdc9b5c9
commit 0bb7d1373f
59 changed files with 228 additions and 241 deletions
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16
passes/pmgen/Makefile.inc
View file

@ -37,14 +37,14 @@ $(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_cascade_pm.h))
# --------------------------------------
OBJS += passes/pmgen/mchp_dsp.o
GENFILES += passes/pmgen/mchp_dsp_pm.h
GENFILES += passes/pmgen/mchp_dsp_CREG_pm.h
GENFILES += passes/pmgen/mchp_dsp_cascade_pm.h
passes/pmgen/mchp_dsp.o: passes/pmgen/mchp_dsp_pm.h passes/pmgen/mchp_dsp_CREG_pm.h passes/pmgen/mchp_dsp_cascade_pm.h
$(eval $(call add_extra_objs,passes/pmgen/mchp_dsp_pm.h))
$(eval $(call add_extra_objs,passes/pmgen/mchp_dsp_CREG_pm.h))
$(eval $(call add_extra_objs,passes/pmgen/mchp_dsp_cascade_pm.h))
OBJS += passes/pmgen/microvhip.o
GENFILES += passes/pmgen/microchip_dsp_pm.h
GENFILES += passes/pmgen/microchip_dsp_CREG_pm.h
GENFILES += passes/pmgen/microchip_dsp_cascade_pm.h
passes/pmgen/microchip_dsp.o: passes/pmgen/microchip_dsp_pm.h passes/pmgen/microchip_dsp_CREG_pm.h passes/pmgen/microchip_dsp_cascade_pm.h
$(eval $(call add_extra_objs,passes/pmgen/microchip_dsp_pm.h))
$(eval $(call add_extra_objs,passes/pmgen/microchip_dsp_CREG_pm.h))
$(eval $(call add_extra_objs,passes/pmgen/microchip_dsp_cascade_pm.h))
# --------------------------------------

115
passes/pmgen/mchp_dsp.cc → passes/pmgen/microchip_dsp.cc
View file

@ -16,25 +16,25 @@ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/yosys.h"
#include <deque>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
#include "passes/pmgen/mchp_dsp_pm.h"
#include "passes/pmgen/mchp_dsp_CREG_pm.h"
#include "passes/pmgen/mchp_dsp_cascade_pm.h"
#include "passes/pmgen/microchip_dsp_CREG_pm.h"
#include "passes/pmgen/microchip_dsp_cascade_pm.h"
#include "passes/pmgen/microchip_dsp_pm.h"
void mchp_dsp_pack(mchp_dsp_pm &pm)
void microchip_dsp_pack(microchip_dsp_pm &pm)
{
auto &st = pm.st_mchp_dsp_pack;
auto &st = pm.st_microchip_dsp_pack;
log("Analysing %s.%s for MCHP MACC_PA packing.\n", log_id(pm.module), log_id(st.dsp));
log("Analysing %s.%s for Microchip MACC_PA packing.\n", log_id(pm.module), log_id(st.dsp));
Cell *cell = st.dsp;
//pack pre-adder
// pack pre-adder
if (st.preAdderStatic) {
SigSpec &pasub = cell->connections_.at(ID(PASUB));
log(" static PASUB preadder %s (%s)\n", log_id(st.preAdderStatic), log_id(st.preAdderStatic->type));
@ -42,8 +42,7 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
bool B_SIGNED = st.preAdderStatic->getParam(ID::A_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED);
st.sigD.extend_u0(18, D_SIGNED);
if (st.moveBtoA)
{
if (st.moveBtoA) {
cell->setPort(ID::A, st.sigA); // if pre-adder feeds into A, original sigB will be moved to port A
}
cell->setPort(ID::B, st.sigB);
@ -59,7 +58,7 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
pm.autoremove(st.preAdderStatic);
}
//pack post-adder
// pack post-adder
if (st.postAdderStatic) {
log(" postadder %s (%s)\n", log_id(st.postAdderStatic), log_id(st.postAdderStatic->type));
SigSpec &sub = cell->connections_.at(ID(SUB));
@ -73,28 +72,25 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
log_assert(!"strange post-adder type");
if (st.useFeedBack) {
cell->setPort(ID(CDIN_FDBK_SEL), {State::S0, State::S1});
cell->setPort(ID(CDIN_FDBK_SEL), {State::S0, State::S1});
} else {
st.sigC.extend_u0(48, st.postAdderStatic->getParam(ID::A_SIGNED).as_bool());
cell->setPort(ID::C, st.sigC);
cell->setPort(ID::C, st.sigC);
}
pm.autoremove(st.postAdderStatic);
}
// pack registers
if (st.clock != SigBit())
{
if (st.clock != SigBit()) {
cell->setPort(ID::CLK, st.clock);
// function to absorb a register
auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport, IdString bypass) {
auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) {
// input/output ports
SigSpec D = ff->getPort(ID::D);
SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
@ -118,21 +114,19 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
// enables are all active high
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
}
else {
} else {
// enables are all active high
cell->setPort(ceport, State::S1);
cell->setPort(ceport, State::S1);
}
// bypass set to 0
cell->setPort(bypass, State::S0);
cell->setPort(bypass, State::S0);
for (auto c : Q.chunks()) {
auto it = c.wire->attributes.find(ID::init);
if (it == c.wire->attributes.end())
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
for (int i = c.offset; i < c.offset + c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
}
@ -164,7 +158,7 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
} else {
f(D, st.ffD, ID(D_EN), ID(D_SRST_N), ID(D_BYPASS));
}
pm.add_siguser(D, cell);
cell->setPort(ID::D, D);
}
@ -189,29 +183,27 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
SigSpec P = st.sigP;
if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
P.append(pm.module->addWire(NEW_ID, 48 - GetSize(P)));
cell->setPort(ID::P, P);
pm.blacklist(cell);
}
// For packing cascaded DSPs
void mchp_dsp_packC(mchp_dsp_CREG_pm &pm)
void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
{
auto &st = pm.st_mchp_dsp_packC;
auto &st = pm.st_microchip_dsp_packC;
log_debug("Analysing %s.%s for MCHP DSP packing (REG_C).\n", log_id(pm.module), log_id(st.dsp));
log_debug("Analysing %s.%s for Microchip DSP packing (REG_C).\n", log_id(pm.module), log_id(st.dsp));
log_debug("ffC: %s\n", log_id(st.ffC, "--"));
Cell *cell = st.dsp;
if (st.clock != SigBit())
{
if (st.clock != SigBit()) {
cell->setPort(ID::CLK, st.clock);
// same function as above, used for the last CREG we need to absorb
auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport, IdString bypass) {
auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) {
// input/output ports
SigSpec D = ff->getPort(ID::D);
SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
@ -240,18 +232,17 @@ void mchp_dsp_packC(mchp_dsp_CREG_pm &pm)
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
} else {
// enables are all active high
cell->setPort(ceport, State::S1);
cell->setPort(ceport, State::S1);
}
// bypass set to 0
cell->setPort(bypass, State::S0);
cell->setPort(bypass, State::S0);
for (auto c : Q.chunks()) {
auto it = c.wire->attributes.find(ID::init);
if (it == c.wire->attributes.end())
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
for (int i = c.offset; i < c.offset + c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
}
@ -260,7 +251,7 @@ void mchp_dsp_packC(mchp_dsp_CREG_pm &pm)
if (st.ffC) {
SigSpec C = cell->getPort(ID::C);
if (st.ffC->type.in(ID($adff), ID($adffe))) {
f(C, st.ffC, ID(C_EN), ID(C_ARST_N), ID(C_BYPASS));
} else {
@ -280,17 +271,17 @@ void mchp_dsp_packC(mchp_dsp_CREG_pm &pm)
pm.blacklist(cell);
}
struct MchpDspPass : public Pass {
MchpDspPass() : Pass("mchp_dsp", "MCHP: pack resources into DSPs") { }
struct MicrochipDspPass : public Pass {
MicrochipDspPass() : Pass("microchip_dsp", "MICROCHIP: pack resources into DSPs") {}
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" mchp_dsp [options] [selection]\n");
log(" microchip_dsp [options] [selection]\n");
log("\n");
log("Pack input registers 'A', 'B', 'C', and 'D' (with optional enable/reset),\n");
log("output register 'P' (with optional enable/reset), pre-adder and/or post-adder into\n");
log("MCHP DSP resources.\n");
log("Microchip DSP resources.\n");
log("\n");
log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n");
log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n");
@ -303,24 +294,23 @@ struct MchpDspPass : public Pass {
log("implement wide multipliers). Cascade chains are limited to a mazimum length \n");
log("of 24 cells, corresponding to PolarFire (pf) devices.\n");
log("\n");
log("This pass is a no-op if the scratchpad variable 'mchp_dsp.multonly' is set\n");
log("This pass is a no-op if the scratchpad variable 'microchip_dsp.multonly' is set\n");
log("to 1.\n");
log("\n");
log("\n");
log(" -family {pf}\n");
log(" -family {polarfire}\n");
log(" select the family to target\n");
log(" default: pf\n");
log(" default: polarfire\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing MCHP_DSP pass (pack resources into DSPs).\n");
log_header(design, "Executing MICROCHIP_DSP pass (pack resources into DSPs).\n");
std::string family = "pf";
std::string family = "polarfire";
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if ((args[argidx] == "-family") && argidx+1 < args.size()) {
for (argidx = 1; argidx < args.size(); argidx++) {
if ((args[argidx] == "-family") && argidx + 1 < args.size()) {
family = args[++argidx];
continue;
}
@ -330,7 +320,7 @@ struct MchpDspPass : public Pass {
for (auto module : design->selected_modules()) {
if (design->scratchpad_get_bool("mchp_dsp.multonly"))
if (design->scratchpad_get_bool("microchip_dsp.multonly"))
continue;
{
@ -338,13 +328,13 @@ struct MchpDspPass : public Pass {
// the "PolarFire FPGA Macro Library Guide"
// Main pattern matching step to capture a DSP cell.
// Match for pre-adder, post-adder, as well as
// Match for pre-adder, post-adder, as well as
// registers 'A', 'B', 'D', and 'P'. Additionally,
// check for an accumulator pattern based on whether
// a post-adder and PREG are both present AND
// if PREG feeds into this post-adder.
mchp_dsp_pm pm(module, module->selected_cells());
pm.run_mchp_dsp_pack(mchp_dsp_pack);
// if PREG feeds into this post-adder.
microchip_dsp_pm pm(module, module->selected_cells());
pm.run_microchip_dsp_pack(microchip_dsp_pack);
}
// Separating out CREG packing is necessary since there
@ -356,18 +346,17 @@ struct MchpDspPass : public Pass {
// PREG of an upstream DSP that had not been visited
// yet
{
mchp_dsp_CREG_pm pm(module, module->selected_cells());
pm.run_mchp_dsp_packC(mchp_dsp_packC);
microchip_dsp_CREG_pm pm(module, module->selected_cells());
pm.run_microchip_dsp_packC(microchip_dsp_packC);
}
// Lastly, identify and utilise PCOUT -> PCIN chains
{
mchp_dsp_cascade_pm pm(module, module->selected_cells());
pm.run_mchp_dsp_cascade();
microchip_dsp_cascade_pm pm(module, module->selected_cells());
pm.run_microchip_dsp_cascade();
}
}
}
} MchpDspPass;
} MicrochipDspPass;
PRIVATE_NAMESPACE_END

4
passes/pmgen/mchp_dsp.pmg → passes/pmgen/microchip_dsp.pmg
View file

@ -16,7 +16,7 @@
// This file describes the main pattern matcher setup (of three total) that
// forms the `mchp_dsp` pass described in mchp_dsp.cc
// forms the `microchip_dsp` pass described in microchip_dsp.cc
// At a high level, it works as follows:
// ( 1) Starting from a DSP cell. Capture DSP configurations as states
// ( 2) Match for pre-adder
@ -31,7 +31,7 @@
// |MULT|------ | adder | +----+
// +----+ \-------/
pattern mchp_dsp_pack
pattern microchip_dsp_pack
state <SigBit> clock
state <SigSpec> sigA sigB sigC sigD sigP

10
passes/pmgen/mchp_dsp_CREG.pmg → passes/pmgen/microchip_dsp_CREG.pmg
View file

@ -16,7 +16,7 @@
// This file describes the second of three pattern matcher setups that
// forms the `mchp_dsp` pass described in mchp_dsp.cc
// forms the `microchip_dsp` pass described in microchip_dsp.cc
// At a high level, it works as follows:
// (1) Starting from a DSP cell that (a) doesn't have a CREG already,
// and (b) uses the 'C' port
@ -24,21 +24,21 @@
// (attached to at most two $mux cells that implement clock-enable or
// reset functionality, using a subpattern discussed below)
// Notes:
// - Running CREG packing after mchp_dsp_pack is necessary since there is no
// - Running CREG packing after microchip_dsp_pack is necessary since there is no
// guarantee that the cell ordering corresponds to the "expected" case (i.e.
// the order in which they appear in the source) thus the possiblity existed
// where a register got packed as a CREG into a downstream DSP, while it should
// have otherwise been a PREG of an upstream DSP that had not been visited.
// yet.
// - The reason this is separated out from the mchp_dsp.pmg file is
// - The reason this is separated out from the microchip_dsp.pmg file is
// for efficiency --- each *.pmg file creates a class of the same basename,
// which when constructed, creates a custom database tailored to the
// pattern(s) contained within. Since the pattern in this file must be
// executed after the pattern contained in mchp_dsp.pmg, it is necessary
// executed after the pattern contained in microchip_dsp.pmg, it is necessary
// to reconstruct this database. Separating the two patterns into
// independent files causes two smaller, more specific, databases.
pattern mchp_dsp_packC
pattern microchip_dsp_packC
udata <std::function<SigSpec(const SigSpec&)>> unextend
state <SigBit> clock

4
passes/pmgen/mchp_dsp_cascade.pmg → passes/pmgen/microchip_dsp_cascade.pmg
View file

@ -16,7 +16,7 @@
// This file describes the third of three pattern matcher setups that
// forms the `mchp_dsp` pass described in mchp_dsp.cc
// forms the `microchip_dsp` pass described in microchip_dsp.cc
// At a high level, it works as follows:
// (1) Starting from a DSP cell that
// (a) CDIN_FDBK_SEL is set to default "00"
@ -32,7 +32,7 @@
// height of a DSP column) with each DSP in each chunk being rewritten
// to use [ABP]COUT -> [ABP]CIN cascading as appropriate
pattern mchp_dsp_cascade
pattern microchip_dsp_cascade
udata <std::function<SigSpec(const SigSpec&)>> unextend
udata <vector<std::tuple<Cell*,int>>> chain longest_chain