mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-23 12:48:54 +00:00
Code Activity

Add synopsys VHDL libs by default in GHDL

Browse source
This commit is contained in:
Akash Levy 2024-09-23 04:05:27 -07:00
parent 2d771a352e
commit 0b8d951493
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
frontends/verific/verific.cc
View file

@ -3766,7 +3766,7 @@ struct VerificPass : public Pass {
// Run command to convert VHDL to Verilog // Run command to convert VHDL to Verilog
std::string top = filename_str.substr(0, std::string(FileSystem::Basename(filename)).find_last_of(".")); std::string top = filename_str.substr(0, std::string(FileSystem::Basename(filename)).find_last_of("."));
std::string outfile = "preqorsor/data/" + top + ".v"; std::string outfile = "preqorsor/data/" + top + ".v";
std::string ghdl_cmd = ghdl_path + " --synth --no-formal --out=verilog " + filename_str + " -e " + top + " > " + outfile; std::string ghdl_cmd = ghdl_path + " --synth --no-formal -fsynopsys --out=verilog " + filename_str + " -e " + top + " > " + outfile;
log("Running command: %s\n", ghdl_cmd.c_str()); log("Running command: %s\n", ghdl_cmd.c_str());
if (system(ghdl_cmd.c_str()) != 0) { if (system(ghdl_cmd.c_str()) != 0) {
verific_error_msg.clear(); verific_error_msg.clear();