Added support for "keep" on modules

README

@@ -273,6 +273,8 @@ Verilog Attributes and non-standard features
 - The "keep" attribute on cells and wires is used to mark objects that should
   never be removed by the optimizer. This is used for example for cells that
   have hidden connections that are not part of the netlist, such as IO pads.
+  Setting the "keep" attribute on a module has the same effect as setting it
+  on all instances of the module.
 
 - The "init" attribute on wires is set by the frontend when a register is
   initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis

kernel/rtlil.h

@@ -857,6 +857,11 @@ public:
 	void check();
 	void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);
 
+	bool has_keep_attr() const {
+		return get_bool_attribute("\\keep") || (module && module->design && module->design->module(type) &&
+				module->design->module(type)->get_bool_attribute("\\keep"));
+	}
+
 	template<typename T> void rewrite_sigspecs(T functor);
 };
 

passes/opt/opt_clean.cc

@@ -48,7 +48,7 @@ void rmunused_module_cells(RTLIL::Module *module, bool verbose)
 				wire2driver.insert(sig, cell);
 			}
 		}
-		if (cell->type == "$memwr" || cell->type == "$assert" || cell->get_bool_attribute("\\keep"))
+		if (cell->type == "$memwr" || cell->type == "$assert" || cell->has_keep_attr())
 			queue.insert(cell);
 		unused.insert(cell);
 	}

passes/opt/opt_share.cc

@@ -196,7 +196,7 @@ struct OptShareWorker
 		if (!ct.cell_known(cell1->type))
 			return cell1 < cell2;
 
-		if (cell1->get_bool_attribute("\\keep") || cell2->get_bool_attribute("\\keep"))
+		if (cell1->has_keep_attr() || cell2->has_keep_attr())
 			return cell1 < cell2;
 
 		bool lt;