mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-26 02:25:35 +00:00
Implement SV structs.
This commit is contained in:
Peter Crozier
parent
aafaeb66df
commit
0b6b47ca67
9 changed files with 508 additions and 203 deletions
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@ -161,6 +161,23 @@ static bool isInLocalScope(const std::string *name)
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return (user_types->count(*name) > 0);
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}
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static AstNode *getTypeDefinitionNode(std::string type_name)
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{
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// return the definition nodes from the typedef statement
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auto user_types = user_type_stack.back();
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log_assert(user_types->count(type_name) > 0);
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auto typedef_node = (*user_types)[type_name];
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log_assert(typedef_node->type == AST_TYPEDEF);
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return typedef_node->children[0];
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}
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static AstNode *copyTypeDefinition(std::string type_name)
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{
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// return a copy of the template from a typedef definition
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auto typedef_node = getTypeDefinitionNode(type_name);
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return typedef_node->clone();
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}
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static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
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{
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auto range = new AstNode(AST_RANGE);
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@ -175,6 +192,35 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
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auto range = makeRange(msb, lsb, isSigned);
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parent->children.push_back(range);
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}
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static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
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{
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if (type_node->range_left >= 0 && type_node->range_right >= 0) {
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// type already restricts the range
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if (range_node) {
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frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
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}
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else {
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range_node = makeRange(type_node->range_left, type_node->range_right, false);
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}
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}
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if (range_node && range_node->children.size() != 2) {
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frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
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}
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return range_node;
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}
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static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
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{
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node->type = AST_MEMORY;
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if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
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// SV array size [n], rewrite as [n-1:0]
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rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
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rangeNode->children.push_back(AstNode::mkconst_int(0, false));
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}
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node->children.push_back(rangeNode);
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}
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%}
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%define api.prefix {frontend_verilog_yy}
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@ -223,12 +269,13 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
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%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
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%token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
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%token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
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%token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE
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%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
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%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
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%type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
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%type <string> type_name
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%type <ast> opt_enum_init
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%type <ast> opt_enum_init enum_type struct_type non_wire_data_type
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%type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
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%type <al> attr case_attr
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@ -281,6 +328,7 @@ design:
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param_decl design |
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localparam_decl design |
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typedef_decl design |
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struct_decl design |
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package design |
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interface design |
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/* empty */;
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@ -520,9 +568,11 @@ package_body:
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;
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package_body_stmt:
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typedef_decl |
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localparam_decl |
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param_decl;
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typedef_decl
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| struct_decl
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| localparam_decl
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| param_decl
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;
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interface:
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TOK_INTERFACE {
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@ -551,7 +601,7 @@ interface_body:
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interface_body interface_body_stmt |;
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interface_body_stmt:
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param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
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param_decl | localparam_decl | typedef_decl | struct_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
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modport_stmt;
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non_opt_delay:
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@ -582,6 +632,7 @@ wire_type_token_list:
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astbuf3->is_custom_type = true;
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astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
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astbuf3->children.back()->str = *$1;
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delete $1;
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};
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wire_type_token_io:
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@ -682,15 +733,9 @@ range_or_multirange:
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non_opt_multirange { $$ = $1; };
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range_or_signed_int:
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range {
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$$ = $1;
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} |
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TOK_INTEGER {
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$$ = new AstNode(AST_RANGE);
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$$->children.push_back(AstNode::mkconst_int(31, true));
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$$->children.push_back(AstNode::mkconst_int(0, true));
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$$->is_signed = true;
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};
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range { $$ = $1; }
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| TOK_INTEGER { $$ = makeRange(); }
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;
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module_body:
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module_body module_body_stmt |
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@ -700,7 +745,7 @@ module_body:
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module_body_stmt:
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task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
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enum_decl |
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enum_decl | struct_decl |
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always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
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checker_decl:
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@ -841,18 +886,7 @@ task_func_port:
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}
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albuf = $1;
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astbuf1 = $2;
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astbuf2 = $3;
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if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
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if (astbuf2) {
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frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions (task/function arguments)");
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} else {
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astbuf2 = new AstNode(AST_RANGE);
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astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
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astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
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}
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}
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if (astbuf2 && astbuf2->children.size() != 2)
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frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
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astbuf2 = checkRange(astbuf1, $3);
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} wire_name | wire_name;
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task_func_body:
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@ -1375,6 +1409,10 @@ single_defparam_decl:
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ast_stack.back()->children.push_back(node);
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};
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/////////
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// enum
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/////////
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enum_type: TOK_ENUM {
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static int enum_count;
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// create parent node for the enum
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@ -1385,31 +1423,39 @@ enum_type: TOK_ENUM {
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// create the template for the names
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astbuf1 = new AstNode(AST_ENUM_ITEM);
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astbuf1->children.push_back(AstNode::mkconst_int(0, true));
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} param_signed enum_base_type '{' enum_name_list '}' { // create template for the enum vars
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auto tnode = astbuf1->clone();
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delete astbuf1;
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astbuf1 = tnode;
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tnode->type = AST_WIRE;
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tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
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// drop constant but keep any range
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delete tnode->children[0];
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tnode->children.erase(tnode->children.begin()); }
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} enum_base_type '{' enum_name_list '}' { // create template for the enum vars
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auto tnode = astbuf1->clone();
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delete astbuf1;
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astbuf1 = tnode;
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tnode->type = AST_WIRE;
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tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
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// drop constant but keep any range
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delete tnode->children[0];
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tnode->children.erase(tnode->children.begin());
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$$ = astbuf1; }
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;
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enum_base_type: int_vec param_range
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| int_atom
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| /* nothing */ {astbuf1->is_reg = true; addRange(astbuf1); }
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enum_base_type: type_atom type_signing
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| type_vec type_signing range { if ($3) astbuf1->children.push_back($3); }
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| /* nothing */ { astbuf1->is_reg = true; addRange(astbuf1); }
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;
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int_atom: TOK_INTEGER {astbuf1->is_reg=true; addRange(astbuf1); } // probably should do byte, range [7:0] here
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type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed
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| TOK_INT { astbuf1->is_reg = true; addRange(astbuf1); } // 2-state signed
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| TOK_BYTE { astbuf1->is_reg = true; addRange(astbuf1, 7, 0); } // 2-state signed
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;
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int_vec: TOK_REG {astbuf1->is_reg = true;}
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| TOK_LOGIC {astbuf1->is_logic = true;}
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type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned
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| TOK_LOGIC { astbuf1->is_logic = true; } // unsigned
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;
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enum_name_list:
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enum_name_decl
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type_signing:
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TOK_SIGNED { astbuf1->is_signed = true; }
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| TOK_UNSIGNED { astbuf1->is_signed = false; }
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| // optional
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;
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enum_name_list: enum_name_decl
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| enum_name_list ',' enum_name_decl
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;
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@ -1448,28 +1494,90 @@ enum_var: TOK_ID {
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}
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;
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enum_decl: enum_type enum_var_list ';' {
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//enum_type creates astbuf1 for use by typedef only
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delete astbuf1;
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}
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enum_decl: enum_type enum_var_list ';' { delete $1; }
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;
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/////////
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// struct
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/////////
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struct_decl: struct_type struct_var_list ';' { delete astbuf2; }
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;
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struct_type: TOK_STRUCT { astbuf2 = new AstNode(AST_STRUCT); } opt_packed '{' struct_member_list '}' { $$ = astbuf2; }
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;
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opt_packed: TOK_PACKED opt_signed_struct
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| { frontend_verilog_yyerror("Only STRUCT PACKED supported at this time"); }
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;
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opt_signed_struct:
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TOK_SIGNED { astbuf2->is_signed = true; }
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| TOK_UNSIGNED
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| // default is unsigned
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;
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struct_member_list: struct_member
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| struct_member_list struct_member
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;
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struct_member: struct_member_type member_name_list ';' { delete astbuf1; }
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;
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member_name_list:
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member_name
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| member_name_list ',' member_name
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;
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member_name: TOK_ID {
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astbuf1->str = $1->substr(1);
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delete $1;
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astbuf2->children.push_back(astbuf1->clone());
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}
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;
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struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_token_list { SET_RULE_LOC(@$, @2, @$); }
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;
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member_type_token_list:
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member_type
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| hierarchical_type_id {
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// use a clone of the typedef definition nodes
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auto template_node = copyTypeDefinition(*$1);
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if (template_node->type != AST_WIRE) {
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frontend_verilog_yyerror("Invalid type for struct member: %s", type2str(template_node->type).c_str());
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}
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template_node->type = AST_STRUCT_ITEM;
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delete astbuf1;
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delete $1;
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astbuf1 = template_node;
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}
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;
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member_type: type_atom type_signing
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| type_vec type_signing range { if ($3) astbuf1->children.push_back($3); }
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;
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struct_var_list: struct_var
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| struct_var_list ',' struct_var
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;
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struct_var: TOK_ID { auto *var_node = astbuf2->clone();
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var_node->str = *$1;
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delete $1;
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ast_stack.back()->children.push_back(var_node);
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}
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;
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/////////
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// wire
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/////////
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wire_decl:
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attr wire_type range {
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albuf = $1;
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astbuf1 = $2;
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astbuf2 = $3;
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if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
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if (astbuf2) {
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frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
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} else {
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astbuf2 = new AstNode(AST_RANGE);
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astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
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astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
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}
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}
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if (astbuf2 && astbuf2->children.size() != 2)
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frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
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astbuf2 = checkRange(astbuf1, $3);
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} delay wire_name_list {
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delete astbuf1;
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if (astbuf2 != NULL)
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@ -1591,19 +1699,9 @@ wire_name:
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if (node->is_input || node->is_output)
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frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
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if (!astbuf2 && !node->is_custom_type) {
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AstNode *rng = new AstNode(AST_RANGE);
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rng->children.push_back(AstNode::mkconst_int(0, true));
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rng->children.push_back(AstNode::mkconst_int(0, true));
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node->children.push_back(rng);
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addRange(node, 0, 0, false);
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}
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node->type = AST_MEMORY;
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auto *rangeNode = $2;
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if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
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// SV array size [n], rewrite as [n-1:0]
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rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
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rangeNode->children.push_back(AstNode::mkconst_int(0, false));
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}
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node->children.push_back(rangeNode);
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rewriteAsMemoryNode(node, $2);
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}
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if (current_function_or_task == NULL) {
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if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
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@ -1651,42 +1749,23 @@ type_name: TOK_ID // first time seen
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typedef_decl:
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TOK_TYPEDEF wire_type range type_name range_or_multirange ';' {
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astbuf1 = $2;
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astbuf2 = $3;
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if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
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if (astbuf2) {
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frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
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} else {
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astbuf2 = new AstNode(AST_RANGE);
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astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
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astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
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}
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}
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if (astbuf2 && astbuf2->children.size() != 2)
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frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
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astbuf2 = checkRange(astbuf1, $3);
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if (astbuf2)
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astbuf1->children.push_back(astbuf2);
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if ($5 != NULL) {
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if (!astbuf2) {
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AstNode *rng = new AstNode(AST_RANGE);
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rng->children.push_back(AstNode::mkconst_int(0, true));
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rng->children.push_back(AstNode::mkconst_int(0, true));
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astbuf1->children.push_back(rng);
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addRange(astbuf1, 0, 0, false);
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}
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astbuf1->type = AST_MEMORY;
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auto *rangeNode = $5;
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if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
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// SV array size [n], rewrite as [n-1:0]
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rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
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rangeNode->children.push_back(AstNode::mkconst_int(0, false));
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}
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astbuf1->children.push_back(rangeNode);
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rewriteAsMemoryNode(astbuf1, $5);
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}
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addTypedefNode($4, astbuf1);
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} |
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TOK_TYPEDEF enum_type type_name ';' {
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addTypedefNode($3, astbuf1);
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}
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addTypedefNode($4, astbuf1); }
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| TOK_TYPEDEF non_wire_data_type type_name ';' { addTypedefNode($3, $2); }
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;
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non_wire_data_type:
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enum_type
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| struct_type
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;
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cell_stmt:
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|
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|
|||
Loading…
Add table
Add a link
Reference in a new issue