mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 13:29:12 +00:00 
			
		
		
		
	Added DFFSR cell to techlibs/cmos/cmos_cells.lib
This commit is contained in:
		
							parent
							
								
									0efe16f118
								
							
						
					
					
						commit
						0b4a64ac6a
					
				
					 2 changed files with 26 additions and 0 deletions
				
			
		| 
						 | 
					@ -29,4 +29,18 @@ library(demo) {
 | 
				
			||||||
    pin(Q) { direction: output;
 | 
					    pin(Q) { direction: output;
 | 
				
			||||||
              function: "IQ"; }
 | 
					              function: "IQ"; }
 | 
				
			||||||
  }
 | 
					  }
 | 
				
			||||||
 | 
					  cell(DFFSR) {
 | 
				
			||||||
 | 
					    area: 18;
 | 
				
			||||||
 | 
					    ff(IQ, IQN) { clocked_on: C;
 | 
				
			||||||
 | 
					                  next_state: D;
 | 
				
			||||||
 | 
					                      preset: S;
 | 
				
			||||||
 | 
					                       clear: R; }
 | 
				
			||||||
 | 
					    pin(C) { direction: input;
 | 
				
			||||||
 | 
					                 clock: true; }
 | 
				
			||||||
 | 
					    pin(D) { direction: input; }
 | 
				
			||||||
 | 
					    pin(Q) { direction: output;
 | 
				
			||||||
 | 
					              function: "IQ"; }
 | 
				
			||||||
 | 
					    pin(S) { direction: input; }
 | 
				
			||||||
 | 
					    pin(R) { direction: input; }
 | 
				
			||||||
 | 
					  }
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
| 
						 | 
					@ -21,3 +21,15 @@ always @(posedge C)
 | 
				
			||||||
	Q <= D;
 | 
						Q <= D;
 | 
				
			||||||
endmodule
 | 
					endmodule
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					module DFFSR(C, D, Q, S, R);
 | 
				
			||||||
 | 
					input C, D, S, R;
 | 
				
			||||||
 | 
					output reg Q;
 | 
				
			||||||
 | 
					always @(posedge C, posedge S, posedge R)
 | 
				
			||||||
 | 
						if (S)
 | 
				
			||||||
 | 
							Q <= 1'b1;
 | 
				
			||||||
 | 
						else if (R)
 | 
				
			||||||
 | 
							Q <= 1'b0;
 | 
				
			||||||
 | 
						else
 | 
				
			||||||
 | 
							Q <= D;
 | 
				
			||||||
 | 
					endmodule
 | 
				
			||||||
 | 
					
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue