mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-08 20:21:25 +00:00
Code Activity

Added DFFSR cell to techlibs/cmos/cmos_cells.lib

Browse source
This commit is contained in:
Clifford Wolf 2013-10-31 12:27:35 +01:00
parent 0efe16f118
commit 0b4a64ac6a
2 changed files with 26 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

12
techlibs/cmos/cmos_cells.v
View file

@ -21,3 +21,15 @@ always @(posedge C)
Q <= D;
endmodule
module DFFSR(C, D, Q, S, R);
input C, D, S, R;
output reg Q;
always @(posedge C, posedge S, posedge R)
if (S)
Q <= 1'b1;
else if (R)
Q <= 1'b0;
else
Q <= D;
endmodule