mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

cosmetic changes

Browse source
This commit is contained in:
chunlin min 2024-07-08 15:10:44 -04:00
parent af67c745c4
commit 0afb5e28fb
1 changed files with 3 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
techlibs/microchip/synth_microchip.cc
View file

@ -87,7 +87,7 @@ struct SynthMicrochipPass : public ScriptPass {
log(" Run 'abc' with '-D 1' option to enable flip-flop retiming.\n"); log(" Run 'abc' with '-D 1' option to enable flip-flop retiming.\n");
log(" implies -dff.\n"); log(" implies -dff.\n");
log("\n"); log("\n");
log(" -abc\n"); log(" -noabc9\n");
log(" Use classic ABC flow instead of ABC9\n"); log(" Use classic ABC flow instead of ABC9\n");
log("\n"); log("\n");
log("\n"); log("\n");
@ -198,7 +198,7 @@ struct SynthMicrochipPass : public ScriptPass {
nobram = true; nobram = true;
continue; continue;
} }
if (args[argidx] == "-abc") { if (args[argidx] == "-noabc9") {
abc9 = false; abc9 = false;
continue; continue;
} }
@ -481,7 +481,7 @@ struct SynthMicrochipPass : public ScriptPass {
else if (abc9) { else if (abc9) {
std::string abc9_opts; std::string abc9_opts;
// for the if command in abc to specify wire delay between adjects LUTs (default = 0) // for the if command in abc to specify wire delay between adjacent LUTs (default = 0)
// NOTE: should not have 0 wire delay between LUTs, // NOTE: should not have 0 wire delay between LUTs,
// otherwise abc might use LUT2+LUT3 instead of single LUT4 // otherwise abc might use LUT2+LUT3 instead of single LUT4
abc9_opts += " -W 300"; abc9_opts += " -W 300";